公开(公告)号：US20230004855A1

公开(公告)日：2023-01-05

申请号：US17363856

申请日：2021-06-30

Applicant: Texas Instruments Incorporated

Inventor： Mihir Narendra MODY ,  Kumar DESAPPAN ,  Gregory Raymond SHURTZ ,  Jason A.T. JONES

IPC: G06N20/00 ,  G06F9/50

Abstract: Techniques for executing machine learning (ML) models including receiving an indication to execute an ML model on a processing core; determining a resource allocation for executing the ML model on the processing core; determining that a layer of the ML model will use a first amount of the resource, wherein the first amount is more than an amount of the resource allocated; determining that an adaptation may be applied to executing the layer of the ML model; executing the layer of the ML model using the adaptation, wherein executing the layer using the adaptation reduces the first amount of the resource used by the layer as compared to executing the layer without using the adaptation; and outputting a result of the ML model based on the executed layer.

公开(公告)号：US20220391219A1

公开(公告)日：2022-12-08

申请号：US17888533

申请日：2022-08-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishnan GOVINDARAJAN ,  Denis Roland BEAUDOIN ,  Gregory Raymond SHURTZ ,  Santhanakrishnan Badri NARAYANAN ,  Mark Adrian BRYANS ,  Mihir Narendra MODY ,  Jason A.T. JONES ,  Jayant THAKUR

IPC: G06F9/4401 ,  H04L45/00 ,  H04L47/32 ,  G06F13/28 ,  H04L49/351

Abstract: An Ethernet switch and a switch microcontroller or CPU are integrated onto a system-on-a-chip (SoC). The Ethernet switch remains independently operating at full speed even though the remainder of the SoC is being reset or is otherwise nonoperational. The Ethernet switch is on a separated power and clock domain from the remainder of the integrated SoC. A warm reset signal is trapped by control microcontroller (MCU) to allow the switch CPU to isolate the Ethernet switch and save state. When the Ethernet switch is isolated and operating independently, the warm reset request is provided to the other entities on the integrated SoC. When warm reset is completed, the state is restored and the various DMA and flow settings redeveloped in the integrated SoC to allow return to normal operating condition.

公开(公告)号：US20210165744A1

公开(公告)日：2021-06-03

申请号：US17171185

申请日：2021-02-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishnan GOVINDARAJAN ,  Gregory Raymond SHURTZ ,  Mihir Narendra MODY ,  Charles Lance FUOCO ,  Donald E. STEISS ,  Jonathan Elliot BERGSAGEL ,  Jason A.T. JONES

IPC: G06F12/1027 ,  G06F9/455

Abstract: In an example, a device includes a memory and a processor core coupled to the memory via a memory management unit (MMU). The device also includes a system MMU (SMMU) cross-referencing virtual addresses (VAs) with intermediate physical addresses (IPAs) and IPAs with physical addresses (PAs). The device further includes a physical address table (PAT) cross-referencing IPAs with each other and cross-referencing PAs with each other. The device also includes a peripheral virtualization unit (PVU) cross-referencing IPAs with PAs, and a routing circuit coupled to the memory, the SMMU, the PAT, and the PVU. The routing circuit is configured to receive a request comprising an address and an attribute and to route the request through at least one of the SMMU, the PAT, or the PVU based on the address and the attribute.

公开(公告)号：US20200379928A1

公开(公告)日：2020-12-03

申请号：US16995364

申请日：2020-08-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir MODY ,  Niraj NANDAN ,  Hetul SANGHVI ,  Brian CHAE ,  Rajasekhar Reddy ALLU ,  Jason A.T. JONES ,  Anthony LELL ,  Anish REGHUNATH

IPC: G06F13/16 ,  H04N5/765 ,  G06T1/20 ,  G06F13/28

Abstract: A processing accelerator includes a shared memory, and a stream accelerator, a memory-to-memory accelerator, and a common DMA controller coupled to the shared memory. The stream accelerator is configured to process a real-time data stream, and to store stream accelerator output data generated by processing the real-time data stream in the shared memory. The memory-to-memory accelerator is configured to retrieve input data from the shared memory, to process the input data, and to store, in the shared memory, memory-to-memory accelerator output data generated by processing the input data. The common DMA controller is configured to retrieve stream accelerator output data from the shared memory and transfer the stream accelerator output data to memory external to the processing accelerator; and to retrieve the memory-to-memory accelerator output data from the shared memory and transfer the memory-to-memory accelerator output data to memory external to the processing accelerator.