公开(公告)号：US08504882B2

公开(公告)日：2013-08-06

申请号：US12884305

申请日：2010-09-17

Applicant: Peng Li ,  Masashi Shimanouchi ,  Sergey Shumarayev ,  Weiqi Ding ,  Siriram Narayan ,  Daniel Tun Lai Chow ,  Mingde Pan

Inventor： Peng Li ,  Masashi Shimanouchi ,  Sergey Shumarayev ,  Weiqi Ding ,  Siriram Narayan ,  Daniel Tun Lai Chow ,  Mingde Pan

IPC: G06F11/00

CPC classification number: G06F11/267

Abstract: An integrated circuit (“IC”) includes circuitry for use in testing a serial data signal. One such IC includes circuitry for transmitting the serial data signal with optional jitter, optional noise, and/or controllably variable drive strength. One such IC also includes circuitry for receiving the serial data signal and performing a bit error rate (“BER”) analysis in such a signal. Such an IC provides output signals indicative of results of its operations. One such IC operates in various modes to perform or at least emulate functions of an oscilloscope, a bit error rate tester, etc., for testing signals and circuitry with respect to jitter-tolerance, noise-tolerance, etc.

Abstract translation: 集成电路（“IC”）包括用于测试串行数据信号的电路。 一个这样的IC包括用于以可选的抖动，可选的噪声和/或可控地变化的驱动强度来发送串行数据信号的电路。 一个这样的IC还包括用于接收串行数据信号并且在这种信号中执行误码率（“BER”）分析的电路。 这样的IC提供指示其操作结果的输出信号。 一个这样的IC以各种模式运行，以执行或至少模拟示波器，误码率测试仪等的功能，用于测试关于抖动容差，噪声容限等的信号和电路。

公开(公告)号：US08416001B2

公开(公告)日：2013-04-09

申请号：US13083431

申请日：2011-04-08

Applicant: Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Tim Tri Hoang ,  Yanjing Ke

Inventor： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Tim Tri Hoang ,  Yanjing Ke

IPC: H03K3/017 ,  H03K5/04 ,  H03K7/08

CPC classification number: H03K5/1565 ,  H03K3/017 ,  H03K5/12 ,  H03M9/00

Abstract: A transmitter circuit is operable to provide an output signal in response to a first periodic signal. A multiplexer circuit is operable to provide a second periodic signal as a selected signal during a first phase of operation. The multiplexer circuit is operable to provide the output signal of the transmitter circuit as the selected signal during a second phase of operation. A sampler circuit is operable to generate first samples of the selected signal during the first phase of operation. The sampler circuit is operable to generate second samples of the selected signal during the second phase of operation. A duty cycle control circuit is operable to adjust a duty cycle of the first periodic signal based on the first and the second samples.

Abstract translation: 发射机电路可操作以响应于第一周期性信号提供输出信号。 多路复用器电路可操作以在第一操作阶段期间提供作为选定信号的第二周期信号。 多路复用器电路可操作以在第二操作阶段期间将发射机电路的输出信号提供为所选择的信号。 采样器电路可操作以在第一操作阶段产生所选信号的第一采样。 采样器电路可操作以在第二操作阶段期间产生所选信号的第二采样。 占空比控制电路可操作以基于第一和第二采样来调整第一周期信号的占空比。

公开(公告)号：US08290750B1

公开(公告)日：2012-10-16

申请号：US13036437

申请日：2011-02-28

Applicant: Wilson Wong ,  Allen Chan ,  Sergey Shumarayev ,  Thungoc M. Tran ,  Tim Tri Hoang ,  Weiqi Ding

Inventor： Wilson Wong ,  Allen Chan ,  Sergey Shumarayev ,  Thungoc M. Tran ,  Tim Tri Hoang ,  Weiqi Ding

IPC: H03F1/26

CPC classification number: H03K5/19 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/1778

Abstract: Signal detection circuitry for a serial interface oversamples the input—i.e., samples the input multiple times per clock cycle—so that the likelihood of missing a signal is reduced. Sampling may be done with a regenerative latch which has a large bandwidth and can latch a signal at high speed. The amplitude threshold for detection may be programmable, particularly in a programmable device. Thus, between the use of a regenerative latch which is likely to catch any signal that might be present, and the use of oversampling to avoid the problem of sampling at the wrong time, the likelihood of failing to detect a signal is greatly diminished. Logic, such as a state machine, may be used to determine whether the samples captured s do or do not represent a signal. That logic may be programmable, allowing a user to set various parameters for signal detection.

Abstract translation: 串行接口的信号检测电路对输入进行过采样，即每个时钟周期对输入进行多次采样，从而减少信号丢失的可能性。 可以使用具有大带宽的再生锁存器并且可以高速锁存信号来进行采样。 用于检测的幅度阈值可以是可编程的，特别是在可编程器件中。 因此，在可能捕获可能存在的任何信号的再生锁存器的使用之间以及使用过采样以避免在错误时间采样的问题，大大减少了不能检测信号的可能性。 可以使用诸如状态机的逻辑来确定捕获的样本是否或不表示信号。 该逻辑可以是可编程的，允许用户设置用于信号检测的各种参数。

公开(公告)号：US20120072785A1

公开(公告)日：2012-03-22

申请号：US12884923

申请日：2010-09-17

Applicant: Weiqi Ding ,  Mingde Pan ,  Peng Li ,  Sergey Shumarayev ,  Masashi Shimanouchi

Inventor： Weiqi Ding ,  Mingde Pan ,  Peng Li ,  Sergey Shumarayev ,  Masashi Shimanouchi

IPC: G06F11/00

CPC classification number: H04L1/203 ,  G01R31/3171

Abstract: An IC that includes an eye viewer and a BER checker coupled to the eye viewer, where the BER checker receives a serial data signal from the eye viewer, is provided. In one implementation, the BER checker receives the serial data signal from the eye viewer without the serial data signal passing through a deserializer. In one implementation, the BER checker compares the serial data signal against a reference data signal to determine the BER for the serial data signal. In one implementation, the IC includes an IC core coupled to the eye viewer and the BER checker, where the BER checker is outside the IC core. In one implementation, the BER checker is a dedicated BER checker. In one implementation, the BER checker includes an exclusive OR gate, a programmable delay circuit coupled to the exclusive OR gate, and an error counter coupled to the exclusive OR gate.

Abstract translation: 提供了一种IC，其包括耦合到眼睛观察者的眼睛观察器和BER检查器，其中BER检查器从眼睛观察器接收串行数据信号。 在一个实现中，BER检查器从眼睛观察器接收串行数据信号，而不经过串行数据信号通过解串器。 在一个实现中，BER检验器将串行数据信号与参考数据信号进行比较，以确定串行数据信号的BER。 在一个实现中，IC包括耦合到眼睛观察器和BER检查器的IC核心，其中BER检验器在IC核心之外。 在一个实现中，BER检查器是专用的BER检查器。 在一个实现中，BER检查器包括异或门，耦合到异或门的可编程延迟电路和耦合到异或门的错误计数器。

公开(公告)号：US20120072784A1

公开(公告)日：2012-03-22

申请号：US12884305

申请日：2010-09-17

Applicant: Peng Li ,  Masashi Shimanouchi ,  Sergey Shumarayev ,  Weiqi Ding ,  Sriram Narayan ,  Daniel Tun Lai Chow ,  Mingde Pan

Inventor： Peng Li ,  Masashi Shimanouchi ,  Sergey Shumarayev ,  Weiqi Ding ,  Sriram Narayan ,  Daniel Tun Lai Chow ,  Mingde Pan

IPC: G06F11/00

CPC classification number: G06F11/267

Abstract: An integrated circuit (“IC”) may include circuitry for use in testing a serial data signal. The IC may include circuitry for transmitting the serial data signal with optional jitter, optional noise, and/or controllably variable drive strength. The IC may also include circuitry for receiving the serial data signal and performing a bit error rate (“BER”) analysis in such a signal. The IC may provide output signals indicative of results of its operations. The IC can operate in various modes to perform or at least emulate functions of an oscilloscope, a bit error rate tester, etc., for testing signals and circuitry with respect to jitter-tolerance, noise-tolerance, etc.

Abstract translation: 集成电路（“IC”）可以包括用于测试串行数据信号的电路。 IC可以包括用于以可选的抖动，可选的噪声和/或可控地变化的驱动强度发送串行数据信号的电路。 IC还可以包括用于接收串行数据信号并且在这种信号中执行误码率（“BER”）分析的电路。 IC可以提供指示其操作结果的输出信号。 IC可以以各种模式运行，以执行或至少模拟示波器，误码率测试仪等功能，用于在抖动容限，噪声容限等方面测试信号和电路。

公开(公告)号：US08120407B1

公开(公告)日：2012-02-21

申请号：US12642738

申请日：2009-12-18

Applicant: Teng Chow Ooi ,  Eng Huat Lee ,  Chuan Khye Chai ,  Yew Fatt (Edwin) Kok ,  Sergey Shumarayev

Inventor： Teng Chow Ooi ,  Eng Huat Lee ,  Chuan Khye Chai ,  Yew Fatt (Edwin) Kok ,  Sergey Shumarayev

IPC: H03K23/00

CPC classification number: H03K5/135 ,  H03K2005/00286

Abstract: A circuit includes a phase detection circuit and a phase change circuit. The phase detection circuit compares a phase of a first periodic signal to an input signal to generate a gain signal. The phase change circuit provides phase shifts to the first periodic signal in first and second directions when the gain signal has a first value. The phase change circuit increases phase shifts provided to the first periodic signal in the first direction in response to the gain signal changing from the first value to a second value. The phase change circuit provides phase shifts to the first periodic signal in the second direction when the gain signal has the second value that are smaller than the phase shifts provided to the first periodic signal in the first direction when the gain signal has the second value.

Abstract translation: 电路包括相位检测电路和相变电路。 相位检测电路将第一周期性信号的相位与输入信号进行比较，以产生增益信号。 当增益信号具有第一值时，相变电路在第一和第二方向上向第一周期性信号提供相移。 响应于增益信号从第一值改变到第二值，相变电路增加提供给第一周期信号的第一方向的相移。 当增益信号具有小于当增益信号具有第二值时在第一方向上提供给第一周期信号的相移的第二值时，相变电路在第二方向上向第一周期信号提供相移。

公开(公告)号：US07860203B1

公开(公告)日：2010-12-28

申请号：US11725653

申请日：2007-03-19

Applicant: Sergey Shumarayev ,  Wilson Wong ,  Tim Tri Hoang ,  Thungoc M. Tran

Inventor： Sergey Shumarayev ,  Wilson Wong ,  Tim Tri Hoang ,  Thungoc M. Tran

IPC: H04L7/00

CPC classification number: H03L7/087 ,  H04J3/0688 ,  H04L7/033

Abstract: A programmable logic device integrated circuit (“PLD”) includes high-speed serial interface (“HSSI”) circuitry in addition to programmable logic circuitry. The HSSI circuitry includes multiple channels of nominal data-handling circuitry (typically including clock and data recovery (“CDR”) circuitry), and at least one channel of nominal clock management unit (“CMU”) circuitry (typically including phase-locked loop (“PLL”) circuitry or the like). To increase the flexibility with which the channels can be used, the nominal data-handling channels are equipped to alternatively perform CMU-type functions, and the nominal CMU channel is equipped to alternatively perform data-handling functions.

Abstract translation: 可编程逻辑器件集成电路（“PLD”）除了可编程逻辑电路之外还包括高速串行接口（“HSSI”）电路。 HSSI电路包括多个标称数据处理电路（通常包括时钟和数据恢复（“CDR”）电路）的通道，以及标称时钟管理单元（“CMU”）电路的至少一个通道（通常包括锁相环 （“PLL”）电路等）。 为了增加可以使用信道的灵活性，标称数据处理信道被配备为交替执行CMU类型功能，并且标称CMU信道被配备为备选地执行数据处理功能。

公开(公告)号：US07855576B1

公开(公告)日：2010-12-21

申请号：US11407444

申请日：2006-04-19

Applicant: Mei Luo ,  Sergey Shumarayev ,  Thungoc M. Tran ,  Simardeep Maangat

Inventor： Mei Luo ,  Sergey Shumarayev ,  Thungoc M. Tran ,  Simardeep Maangat

IPC: H03K19/0175 ,  H03K19/003

CPC classification number: H03K19/017509 ,  H04L25/0276

Abstract: Methods and apparatus are provided for selectively setting a CM voltage for a transceiver, reducing the effect of current mismatch, and generating a voltage step that can be used for receiver detection. A circuit of the invention can include voltage generator circuitry operable to generate a plurality of voltage signals of substantially different voltages. The circuit can also include multiplexer circuitry with voltage inputs coupled to the voltage signals. The multiplexer circuitry can be operable to select a reference signal from among the voltage inputs. In addition, the circuit can include operational amplifier (“op-amp”) circuitry with a first input coupled to the reference signal and a second input coupled to an output signal of the op-amp circuitry.

Abstract translation: 提供了用于选择性地设置收发器的CM电压的方法和装置，减少电流失配的影响，以及产生可用于接收机检测的电压步骤。 本发明的电路可以包括可操作以产生具有实质上不同电压的多个电压信号的电压发生器电路。 电路还可以包括具有耦合到电压信号的电压输入的多路复用器电路。 多路复用器电路可以用于从电压输入中选择参考信号。 此外，电路可以包括运算放大器（“运算放大器”）电路，其中耦合到参考信号的第一输入和耦合到运放电路的输出信号的第二输入。

公开(公告)号：US07777526B2

公开(公告)日：2010-08-17

申请号：US12134777

申请日：2008-06-06

Applicant: Sergey Shumarayev ,  Thungoc M. Tran ,  Wilson Wong ,  Simardeep Maangat

Inventor： Sergey Shumarayev ,  Thungoc M. Tran ,  Wilson Wong ,  Simardeep Maangat

IPC: H03K19/094

CPC classification number: H03K19/018514 ,  H03F3/45197 ,  H03F2203/45494 ,  H03F2203/45686

Abstract: Signal offset variation caused by transistor variation/mismatch in integrated circuits may be reduced. In one embodiment, a buffer circuit has variable-valued circuit elements. Offset variation measurements are made and the variable-valued circuit elements are calibrated to reduce the measured offset variation. In another embodiment, each amplifying stage of a multi-stage buffer provides variable gain. The total DC gain of the cascade is distributed unevenly across the stages, with more DC gain being provided by amplifier stages at the beginning of the cascade than at the end. An additional pre-amplifier stage can also be provided at the beginning of the cascade.

Abstract translation: 集成电路中晶体管变化/失配引起的信号偏移变化可能会降低。 在一个实施例中，缓冲电路具有可变值电路元件。 进行偏移变化测量，并校准可变值电路元件以减少测量的偏移变化。 在另一个实施例中，多级缓冲器的每个放大级提供可变增益。 级联的总直流增益不均匀地分布在整个级中，在级联开始时比放大器级提供更多的直流增益。 在级联开始时也可以提供一个额外的前级放大器级。

公开(公告)号：US07733982B2

公开(公告)日：2010-06-08

申请号：US12511022

申请日：2009-07-28

Applicant: Wilson Wong ,  Rakesh H. Patel ,  Sergey Shumarayev ,  Tin H. Lai

Inventor： Wilson Wong ,  Rakesh H. Patel ,  Sergey Shumarayev ,  Tin H. Lai

IPC: H03K9/00 ,  H04L27/00

CPC classification number: H04B7/005 ,  H04L25/03006 ,  H04L25/061

Abstract: Systems and methods for adjusting a signal received from a communication path are disclosed. A receiver can receive a signal from a communication path which attenuates at least some frequency components of the signal. The receiver can include an equalization block that adjusts at least some of the frequency content of the received signal, a signal normalization block that provides a normalized signal amplitude and/or a normalized edge slope, and a control block. In one embodiment, the control block controls frequency adjustment in the equalization block for high frequencies but not for low frequencies. For low frequency adjustment, the control block controls the normalized signal amplitude in the signal normalization block. In this manner, controlled adjustment for low frequency content is performed in the signal normalization block.

Abstract translation: 公开了一种用于调整从通信路径接收的信号的系统和方法。 接收机可以接收来自衰减信号的至少一些频率分量的通信路径的信号。 接收机可以包括调整接收信号的频率内容中的至少一些的均衡块，提供归一化信号幅度和/或归一化边沿斜率的信号归一化块以及控制块。 在一个实施例中，控制块控制用于高频而不是低频的均衡块中的频率调整。 对于低频调整，控制块控制信号归一化块中的归一化信号幅度。 以这种方式，在信号归一化块中执行低频内容的受控调整。