公开(公告)号：US06492242B1

公开(公告)日：2002-12-10

申请号：US09609447

申请日：2000-07-03

Applicant: Alex See ,  Cher Liang Randall Cha ,  Shyuz Fong Quek ,  Ting Cheong Ang ,  Wye Boon Loh ,  Sang Yee Loong ,  Jun Song ,  Chua Chee Tee

Inventor： Alex See ,  Cher Liang Randall Cha ,  Shyuz Fong Quek ,  Ting Cheong Ang ,  Wye Boon Loh ,  Sang Yee Loong ,  Jun Song ,  Chua Chee Tee

IPC: H01L2120

CPC classification number: H01L28/40 ,  H01L21/31683

Abstract: A process for forming a high dielectric constant, (High K), layer, for a metal-oxide-metal, capacitor structure, featuring localized oxidation of an underlying metal layer, performed at a temperature higher than the temperature experienced by surrounding structures, has been developed. A first iteration of this process features the use of a laser ablation procedure, performed to a local region of an underlying metal layer, in an oxidizing ambient. The laser ablation procedure creates the desired, high temperature, only at the laser spot, allowing a high K layer to be created at this temperature, while the surrounding structures on a semiconductor substrate, not directly exposed to the laser ablation procedure remain at lower temperatures. A second iteration features the exposure of specific regions of an underlying metal layer, to a UV, or to an I line exposure procedure, performed in an oxidizing ambient, with the regions of an underlying metal layer exposed to the UV or I line procedure, via clear regions in an overlying photolithographic plate. This procedure also results in the formation of a high K layer, on a top portion of the underlying metal layer.

Abstract translation: 在高于周围结构所经历的温度的温度下进行的金属氧化物 - 金属电容器结构的高介电常数（高K）层，其特征在于底层金属层的局部氧化， 已经开发 该方法的第一次迭代的特征在于在氧化环境中使用对底层金属层的局部区域进行的激光烧蚀程序。 激光烧蚀过程仅在激光点产生所需的高温，允许在该温度下产生高K层，而不直接暴露于激光烧蚀过程的半导体衬底上的周围结构保持在较低温度 。 第二次迭代的特征在于在氧化环境中进行的底层金属层的特定区域到UV或I线曝光程序，暴露于UV或I线程序的下面的金属层的区域， 通过覆盖光刻板中的透明区域。 该过程还导致在下面的金属层的顶部上形成高K层。

公开(公告)号：US06275089B1

公开(公告)日：2001-08-14

申请号：US09482048

申请日：2000-01-13

Applicant: Jun Song ,  Ting Cheong Ang ,  Shyue Fong Quek ,  Lap Chan

Inventor： Jun Song ,  Ting Cheong Ang ,  Shyue Fong Quek ,  Lap Chan

IPC: H03K508

CPC classification number: H01L27/0251

Abstract: A transient protection circuit is described which provides electrostatic discharge (ESD) protection for an internal circuit of an IC. The transient protection circuit comprises two Zener diodes connected in series between the input pad and the internal circuit of the IC. A sufficiently large ESD pulse will drive one the two Zener diodes into breakdown mode, thereby reducing the magnitude of the ESD pulse to the remainder of the circuit. Resistive means are paralleled with the Zener diodes to provide a signal path at non-ESD voltages. To help shunt the ESD current away from the internal circuit, PMOS and NMOS transistors are connected in parallel between the positive and the negative voltage supply and their junction is connected to the internal circuit. Negative ESD pulses cause the PMOS transistors to turn on, dumping the ESD energy into the positive voltage supply, while positive ESD pulses cause the NMOS transistors to turn on, dumping the ESD energy into the negative voltage supply. Voltage changes, caused by currents flowing through the resistive means, trigger parasitic SCRs into conduction to provide the bulk of the ESD protection.

Abstract translation: 描述了为IC的内部电路提供静电放电（ESD）保护的瞬态保护电路。 瞬态保护电路包括串联连接在输入焊盘和IC内部电路之间的两个齐纳二极管。 足够大的ESD脉冲将驱动两个齐纳二极管中的一个进入击穿模式，从而将ESD脉冲的幅度减小到电路的其余部分。 电阻性装置与齐纳二极管并联，以在非ESD电压下提供信号路径。 为了有助于将ESD电流从内部电路分流，PMOS和NMOS晶体管并联连接在正电压和负电源之间，它们的结连接到内部电路。 负ESD脉冲导致PMOS晶体管导通，将ESD能量转储到正电压源中，而正的ESD脉冲使NMOS晶体管导通，将ESD能量转储到负电源。 由电流流过电阻的电流引起的电压变化会将寄生的SCR触发导通，以提供大量的ESD保护。

公开(公告)号：US06258677B1

公开(公告)日：2001-07-10

申请号：US09409875

申请日：1999-10-01

Applicant: Ting Cheong Ang ,  Shyue Fong Quek ,  Sang Yee Loong ,  Jun Song

Inventor： Ting Cheong Ang ,  Shyue Fong Quek ,  Sang Yee Loong ,  Jun Song

IPC: H01L21336

CPC classification number: H01L29/0847 ,  H01L21/76264 ,  H01L21/76278 ,  H01L21/76283 ,  H01L21/823878 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66651

Abstract: A method of fabricating a transistor, comprising the following steps. A silicon semiconductor structure having spaced, raised, wedge-shaped dielectric isolation regions defining an active region there between is provided. Epitaxial silicon is grown over the active area to form an SEG region. A dummy gate is formed over the SEG region. Raised epitaxial silicon layers are grown over the SEG region adjacent the dummy gate. The dummy gate is removed, exposing the interior side walls of the raised epitaxial silicon layers. Sidewall spacers are formed on the exposed sidewalls of the raised epitaxial silicon layers. A gate oxide layer is grown over the SEG region and between the sidewall spacers of the raised epitaxial silicon layers. A layer of polysilicon is deposited over the structure and is planarized to form a gate conductor over the SEG region and between the sidewall spacers of the raised epitaxial silicon layers. The sidewall spacers are removed. No HDP process trench fill is required to form the STIs and no CMP process is required to planarized the STIs.

Abstract translation: 一种制造晶体管的方法，包括以下步骤。 提供了具有限定其间的有源区域的具有间隔开的凸起的楔形介电隔离区域的硅半导体结构。 在活性区域上生长外延硅以形成SEG区域。 在SEG区域上形成一个虚拟门。 凸起的外延硅层生长在与虚拟栅极相邻的SEG区域上。 去除虚拟栅极，暴露凸起的外延硅层的内侧壁。 在凸起的外延硅层的暴露的侧壁上形成侧壁间隔物。 栅极氧化物层生长在SEG区域上并且在凸起的外延硅层的侧壁间隔物之间​​。 在该结构上沉积一层多晶硅，并将其平坦化，以在SEG区域和凸出的外延硅层的侧壁间隔物之间​​形成栅极导体。 去除侧壁间隔物。 不需要HDP工艺沟槽填充来形成STI，并且不需要CMP工艺来平坦化STI。

公开(公告)号：US06248618B1

公开(公告)日：2001-06-19

申请号：US09415246

申请日：1999-10-12

Applicant: Shyue Fong Quek ,  Ting Cheong Ang ,  Puay Ing Ong ,  Sang Yee Loong

Inventor： Shyue Fong Quek ,  Ting Cheong Ang ,  Puay Ing Ong ,  Sang Yee Loong

IPC: H01L218238

CPC classification number: H01L21/823857 ,  Y10S438/981

Abstract: A method of forming thick and thin gate oxides comprising the following steps. A silicon semiconductor substrate having first and second active areas separated by shallow isolation trench regions is provided. Oxide growth is selectively formed over the first active area by UV oxidation to form a first gate oxide layer having a first predetermined thickness. The first and second active areas are then simultaneously oxidized whereby the first predetermined thickness of the first gate oxide layer is increased to a second predetermined thickness and a second gate oxide layer having a predetermined thickness is formed in the second active area. The second predetermined thickness of the first oxide layer in the first active area is greater than the predetermined thickness of the second oxide layer in the second active area.

Abstract translation: 一种形成厚薄的栅极氧化物的方法，包括以下步骤。 提供具有由浅隔离沟槽区域隔开的第一和第二有源区的硅半导体衬底。 通过UV氧化在第一有源区上选择性地形成氧化物生长，以形成具有第一预定厚度的第一栅氧化层。 然后，第一和第二有源区域被同时氧化，由此第一栅极氧化物层的第一预定厚度增加到第二预定厚度，并且在第二有源区域中形成具有预定厚度的第二栅极氧化物层。 第一有源区中的第一氧化物层的第二预定厚度大于第二有源区中第二氧化物层的预定厚度。

公开(公告)号：US20120211863A1

公开(公告)日：2012-08-23

申请号：US13456079

申请日：2012-04-25

Applicant: Ting Cheong Ang

Inventor： Ting Cheong Ang

IPC: H01L29/06

CPC classification number: H01L21/76224

Abstract: A semiconductor structure includes a semiconductor substrate with a substrate region and a trench extending into the surface region of the semiconductor substrate. The trench includes sidewalls, a bottom and a depth. The semiconductor structure further includes a trench liner overlying the bottom and the sidewalls of the trench. The semiconductor structure also includes a shallow trench isolation structure filling at least the depth of the trench. The shallow trench isolation structure is formed from alternating layers of silicon nitride and high-density plasma oxide.

Abstract translation: 半导体结构包括具有衬底区域的半导体衬底和延伸到半导体衬底的表面区域中的沟槽。 沟槽包括侧壁，底部和深度。 半导体结构还包括覆盖沟槽的底部和侧壁的沟槽衬垫。 半导体结构还包括至少填充沟槽的深度的浅沟槽隔离结构。 浅沟槽隔离结构由氮化硅和高密度等离子体氧化物的交替层形成。

公开(公告)号：US08187950B2

公开(公告)日：2012-05-29

申请号：US12258366

申请日：2008-10-24

Applicant: Ting Cheong Ang

Inventor： Ting Cheong Ang

IPC: H01L21/76

CPC classification number: H01L21/76224

Abstract: A method of forming a semiconductor structure is provided. The method includes providing a semiconductor substrate with a substrate region. The method also includes forming a pad oxide layer overlying the substrate region. The method additionally includes forming a stop layer overlying the pad oxide layer. Furthermore, the method includes patterning the stop layer and the pad oxide layer to expose a portion of the substrate region. In addition, the method includes forming a trench within an exposed portion of the substrate region, the trench having sidewalls and a bottom and a height. Also, the method includes depositing alternating layers of oxide and silicon nitride to at least fill the trench, the oxide being deposited by an HDP-CVD process. The method additionally includes performing a planarization process to remove a portion of the silicon nitride and oxide layers. In addition, the method includes removing the pad oxide and stop layers.

Abstract translation: 提供一种形成半导体结构的方法。 该方法包括提供具有衬底区域的半导体衬底。 该方法还包括形成覆盖衬底区域的衬垫氧化物层。 该方法还包括形成覆盖衬垫氧化物层的阻挡层。 此外，该方法包括图案化停止层和衬垫氧化物层以暴露衬底区域的一部分。 此外，该方法包括在衬底区域的暴露部分内形成沟槽，沟槽具有侧壁，底部和高度。 此外，该方法包括沉积氧化物和氮化硅的交替层以至少填充沟槽，氧化物通过HDP-CVD工艺沉积。 该方法另外包括执行平坦化处理以去除一部分氮化硅和氧化物层。 此外，该方法包括去除衬垫氧化物并停止层。

公开(公告)号：US20090075454A1

公开(公告)日：2009-03-19

申请号：US12273323

申请日：2008-11-18

Applicant: Ting Cheong Ang

Inventor： Ting Cheong Ang

IPC: H01L21/76

CPC classification number: H01L21/76224

Abstract: A method of performing an STI gapfill process for semiconductor devices is provided. In a specific embodiment of the invention, the method includes forming an stop layer overlying a substrate. In addition, the method includes forming a trench within the substrate, with the trench having sidewalls, a bottom, and a depth. The method additionally includes forming a liner within the trench, the liner lining the sidewalls and bottom of the trench. Furthermore, the method includes filling the trench to a first depth with a first oxide. The first oxide is filled using a spin-on process. The method also includes performing a first densification process on the first oxide within the trench. In addition, the method includes depositing a second oxide within the trench using an HDP process to fill at least the entirety of the trench. The method also includes performing a second densification process on the first and second oxides within the trench.

Abstract translation: 提供了一种用于半导体器件的STI间隙填充处理的方法。 在本发明的具体实施方案中，该方法包括形成覆盖衬底的阻挡层。 此外，该方法包括在衬底内形成沟槽，其中沟槽具有侧壁，底部和深度。 该方法还包括在沟槽内形成衬垫，衬垫衬在沟槽的侧壁和底部。 此外，该方法包括用第一氧化物将沟槽填充到第一深度。 使用旋涂工艺填充第一氧化物。 该方法还包括对沟槽内的第一氧化物进行第一致密化处理。 另外，该方法包括使用HDP工艺在沟槽内沉积第二氧化物以填充至少整个沟槽。 该方法还包括对沟槽内的第一和第二氧化物进行第二致密化处理。

公开(公告)号：US20070254453A1

公开(公告)日：2007-11-01

申请号：US11549116

申请日：2006-10-13

Applicant: Ting Cheong Ang

Inventor： Ting Cheong Ang

IPC: H01L21/76

CPC classification number: H01L21/76232

Abstract: A method of forming a graded trench for a shallow trench isolation region is provided. The method includes providing a semiconductor substrate with a substrate region. The method further includes forming a pad oxide layer overlying the substrate region. Additionally, the method includes forming an etch stop layer overlying the pad oxide layer. The method further includes patterning the etch stop layer and the pad oxide layer to expose a portion of the substrate region. In addition, the method includes forming a trench within an exposed portion of the substrate region, the trench having sidewalls and a bottom and a first depth. The method additionally includes forming a dielectric layer overlying the trench sidewalls, the trench bottom, and mesa regions adjacent to the trench. The method further includes removing a first portion of the dielectric layer from the trench bottom to expose the substrate region with a second portion of the dielectric layer remaining on the sidewalls of the trench. In addition, the method includes etching the substrate region to increase the depth of at least a portion of the trench to a second depth. Also, the method includes removing the second portion of the dielectric layer from the trench.

Abstract translation: 提供了形成浅沟槽隔离区域的分级沟槽的方法。 该方法包括提供具有衬底区域的半导体衬底。 该方法还包括形成覆盖衬底区域的衬垫氧化物层。 另外，该方法包括形成覆盖衬垫氧化物层的蚀刻停止层。 该方法还包括图案化蚀刻停止层和衬垫氧化物层以暴露衬底区域的一部分。 此外，该方法包括在衬底区域的暴露部分内形成沟槽，沟槽具有侧壁和底部以及第一深度。 该方法另外包括形成覆盖沟槽侧壁，沟槽底部和与沟槽相邻的台面区域的介电层。 该方法还包括从沟槽底部去除电介质层的第一部分以暴露衬底区域，其中介电层的第二部分保留在沟槽的侧壁上。 此外，该方法包括蚀刻衬底区域以将沟槽的至少一部分的深度增加到第二深度。 此外，该方法包括从沟槽去除电介质层的第二部分。

公开(公告)号：US06963113B2

公开(公告)日：2005-11-08

申请号：US10915670

申请日：2004-08-10

Applicant: Ting Cheong Ang ,  Sang Yee Loong ,  Shyue Fong Quek ,  Jun Song

Inventor： Ting Cheong Ang ,  Sang Yee Loong ,  Shyue Fong Quek ,  Jun Song

IPC: H01L21/336 ,  H01L29/786 ,  H01L29/76

CPC classification number: H01L29/66772 ,  H01L29/78615

Abstract: A new method for forming a silicon-on-insulator MOSFET while eliminating floating body effects is described. A silicon-on-insulator substrate is provided comprising a silicon semiconductor substrate underlying an oxide layer underlying a silicon layer. A first trench is etched partially through the silicon layer and not to the underlying oxide layer. Second trenches are etched fully through the silicon layer to the underlying oxide layer wherein the second trenches separate active areas of the semiconductor substrate and wherein one of the first trenches lies within each of the active areas. The first and second trenches are filled with an insulating layer. Gate electrodes and associated source and drain regions are formed in and on the silicon layer in each active area. An interlevel dielectric layer is deposited overlying the gate electrodes. First contacts are opened through the interlevel dielectric layer to the underlying source and drain regions. A second contact opening is made through the interlevel dielectric layer in each of the active regions wherein the second contact opening contacts both the first trench and one of the second trenches. The first and second contact openings are filled with a conducting layer to complete formation of a silicon-on-insulator device in the fabrication of integrated circuits.

Abstract translation: 描述了一种在消除浮体效应的同时形成绝缘体上硅MOSFET的新方法。 提供了一种绝缘体上硅衬底，其包括位于硅层下面的氧化物层下面的硅半导体衬底。 第一沟槽部分地被蚀刻穿过硅层而不是蚀刻到下面的氧化物层。 第二沟槽被完全蚀刻通过硅层到下面的氧化物层，其中第二沟槽分离半导体衬底的有源区域，并且其中第一沟槽中的一个位于每个有源区域内。 第一和第二沟槽填充有绝缘层。 栅极电极和相关的源极和漏极区域形成在每个有源区域中的硅层中和硅层上。 沉积覆盖栅电极的层间电介质层。 第一触点通过层间介质层开放到下面的源极和漏极区域。 在每个有源区域中通过层间电介质层形成第二接触开口，其中第二接触开口接触第一沟槽和第二沟槽中的一个沟槽。 第一和第二接触开口填充有导电层，以在集成电路的制造中完成绝缘体上硅器件的形成。

公开(公告)号：US06815823B2

公开(公告)日：2004-11-09

申请号：US10679736

申请日：2003-10-06

Applicant: Young-Way Teh ,  Victor Seng Keong Lim ,  Ting Cheong Ang

Inventor： Young-Way Teh ,  Victor Seng Keong Lim ,  Ting Cheong Ang

IPC: H01L2348

CPC classification number: H01L23/5226 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/76804 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A new method and structure is provided for the creation of interconnect lines. The cross section of the interconnect lines of the invention, taken in a plane that is perpendicular to the longitudinal direction of the interconnect lines, is a triangle as opposed to the conventional square or rectangular cross section of interconnect lines.

Abstract translation: 提供了一种新的方法和结构来创建互连线。 在与互连线的纵向方向垂直的平面中截取的本发明的互连线的横截面是与传统的互连线的矩形或矩形横截面相反的三角形。