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公开(公告)号：US07193884B2
公开(公告)日：2007-03-20
申请号：US11280170
申请日：2005-11-17
IPC分类号： G11C11/24
CPC分类号： G11C11/4094 , G11C7/12 , G11C7/18 , G11C11/4074 , G11C11/4097 , G11C2211/4013 , H01L27/0207 , H01L27/10882
摘要： A write command is inputted from an outside, voltages of bit lines become VDL and VSS, and a voltage in accordance with a threshold voltage (LVT: low threshold voltage, MVT: mid threshold voltage, HVT: high threshold voltage) of a memory cell transistor is written into a storage node of a capacitor via the memory cell transistor. Thereafter, when a plate line connected to a plate side of the capacitor is driven from voltage VPL to voltage VPH and the voltage of the storage node is increased due to coupling, the voltage VDL of the bit line is reduced to the voltage VDP, and the voltage excessively written into the storage node is reduced in accordance with a level of a threshold voltage of the memory cell transistor, thereby reducing a variation in the voltage of the storage node due to a variation in the threshold voltage.
摘要翻译： 从外部输入写命令，位线的电压变为VDL和VSS，以及根据存储单元的阈值电压（LVT：低阈值电压，MVT：中间阈值电压，HVT：高阈值电压）的电压 晶体管经由存储单元晶体管写入电容器的存储节点。 此后，当连接到电容器的板侧的板线从电压VPL驱动到电压VPH并且存储节点的电压由于耦合而增加时，位线的电压VDL被降低到电压VDP，并且 根据存储单元晶体管的阈值电压的电平降低过度写入存储节点的电压，从而减小由于阈值电压的变化引起的存储节点的电压的变化。
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公开(公告)号：US20070038919A1
公开(公告)日：2007-02-15
申请号：US11495550
申请日：2006-07-31
IPC分类号： G11C29/00
CPC分类号： G06F11/1044 , G11C2029/0409
摘要： A semiconductor memory device capable of achieving a sufficient operating margin without increasing an area penalty even in the case of miniaturization is provided. An error correction system composed of a data bit of 64 bits and a check bit of 9 bits is introduced to a memory array such as DRAM, and an error correction code circuit required therein is disposed near a sense amplifier array. In addition to normal memory arrays composed of such memory arrays, a redundant memory array having a sense amplifier array and an error correction code circuit adjacent thereto is provided in a chip. By this means, the error which occurs in the manufacture can be replaced. Also, the error correction code circuit corrects the error at the time of an activate command and stores the check bit at the time of a pre-charge command.
摘要翻译： 提供了即使在小型化的情况下也能够实现足够的操作余量而不增加面积损失的半导体存储器件。 将由64位的数据位和9位的校验位构成的纠错系统引入到诸如DRAM的存储器阵列中，并且其中需要的纠错码电路设置在读出放大器阵列附近。 除了由这种存储器阵列组成的常规存储器阵列之外，在芯片中提供了具有读出放大器阵列和与其相邻的纠错码电路的冗余存储器阵列。 通过这种方式，可以更换制造过程中发生的错误。 此外，纠错码电路校正了激活命令时的错误，并且在预充电命令时存储检查位。
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公开(公告)号：US07619911B2
公开(公告)日：2009-11-17
申请号：US10579911
申请日：2003-11-21
申请人： Satoru Hanzawa , Junji Shigeta , Shinichiro Kimura , Takeshi Sakata , Riichiro Takemura , Kazuhiko Kajigaya
发明人： Satoru Hanzawa , Junji Shigeta , Shinichiro Kimura , Takeshi Sakata , Riichiro Takemura , Kazuhiko Kajigaya
IPC分类号： G11C15/00
CPC分类号： G11C15/04 , G11C15/043
摘要： In a memory array structured of memory cells using a storage circuit STC and a comparator CP, either one electrode of a source electrode or a drain electrode of a transistor, whose gate electrode is connected to a search line, of a plurality of transistors structuring the comparator CP is connected to a match line HMLr precharged to a high voltage. Further, a match detector MDr is arranged on a match line LMLr precharged to a low voltage to discriminate a comparison signal voltage generated at the match line according to the comparison result of data. According to such memory array structure and operation, comparison operation can be performed at low power and at high speed while influence of search-line noise is avoided in a match line pair. Therefore, a low power content addressable memory which allows search operation at high speed can be realized.
摘要翻译： 在使用存储电路STC和比较器CP的存储器单元构成的存储器阵列中，将栅电极连接到搜索线的晶体管的源电极或漏电极的一个电极，构成 比较器CP连接到预充电到高电压的匹配线HMLr。 此外，匹配检测器MDr布置在预充电到低电压的匹配线LMLr上，以根据数据的比较结果来识别在匹配线处产生的比较信号电压。 根据这种存储器阵列结构和操作，可以在低功率和高速度下执行比较操作，同时在匹配线对中避免搜索线噪声的影响。 因此，可以实现允许高速搜索操作的低功率内容可寻址存储器。
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公开(公告)号：US20060193160A1
公开(公告)日：2006-08-31
申请号：US11354131
申请日：2006-02-15
IPC分类号： G11C15/00
CPC分类号： G11C15/04 , G11C15/043
摘要： Control clocks of different phases are distributed to a memory array divided into multiple banks, and processing of entries and search keys (read and write operations and search operation) is performed at different phases. The memory array divided into banks is further divided into smaller arrays, that is, sub-arrays, and a sense amplifier in a read-write-search circuit block is shared by the two sub-arrays. In this case, a so-called open bit line structure in which each one bit line is connected from both sub-arrays to a sense amplifier is adopted. The same look-up table is registered to multiple banks, successively inputted search keys are sequentially inputted to the multiple banks, and the search operation is carried out in synchronization with the control clocks of different phases.
摘要翻译： 将不同相位的控制时钟分配到划分为多个存储体的存储器阵列，并且在不同阶段执行条目和搜索关键字的处理（读取和写入操作和搜索操作）。 划分为存储体的存储器阵列进一步分成较小的阵列，即子阵列，并且读写搜索电路块中的读出放大器由两个子阵列共享。 在这种情况下，采用所谓的开放位线结构，其中每个位线都从两个子阵列连接到读出放大器。 相同的查找表被注册到多个存储体，连续输入的搜索键被顺序地输入到多个存储体，并且与不同相位的控制时钟同步地执行搜索操作。
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公开(公告)号：US07388768B2
公开(公告)日：2008-06-17
申请号：US11354131
申请日：2006-02-15
IPC分类号： G11C15/00
CPC分类号： G11C15/04 , G11C15/043
摘要： Control clocks of different phases are distributed to a memory array divided into multiple banks, and processing of entries and search keys (read and write operations and search operation) is performed at different phases. The memory array divided into banks is further divided into smaller arrays, that is, sub-arrays, and a sense amplifier in a read-write-search circuit block is shared by the two sub-arrays. In this case, a so-called open bit line structure in which each one bit line is connected from both sub-arrays to a sense amplifier is adopted. The same look-up table is registered to multiple banks, successively inputted search keys are sequentially inputted to the multiple banks, and the search operation is carried out in synchronization with the control clocks of different phases.
摘要翻译： 将不同相位的控制时钟分配到划分为多个存储体的存储器阵列，并且在不同阶段执行条目和搜索关键字的处理（读取和写入操作和搜索操作）。 划分为存储体的存储器阵列进一步分成较小的阵列，即子阵列，并且读写搜索电路块中的读出放大器由两个子阵列共享。 在这种情况下，采用所谓的开放位线结构，其中每个位线都从两个子阵列连接到读出放大器。 相同的查找表被注册到多个存储体，连续输入的搜索键被顺序地输入到多个存储体，并且与不同相位的控制时钟同步地执行搜索操作。
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公开(公告)号：US20070274144A1
公开(公告)日：2007-11-29
申请号：US10579911
申请日：2003-11-21
申请人： Satoru Hanzawa , Junji Shigeta , Shinichiro Kimura , Takeshi Sakata , Riichiro Takemura , Kazuhiko Kajigaya
发明人： Satoru Hanzawa , Junji Shigeta , Shinichiro Kimura , Takeshi Sakata , Riichiro Takemura , Kazuhiko Kajigaya
IPC分类号： G11C7/00
CPC分类号： G11C15/04 , G11C15/043
摘要： In a memory array structured of memory cells using a storage circuit STC and a comparator CP, either one electrode of a source electrode or a drain electrode of a transistor, whose gate electrode is connected to a search line, of a plurality of transistors structuring the comparator CP is connected to a match line HMLr precharged to a high voltage. Further, a match detector MDr is arranged on a match line LMLr precharged to a low voltage to discriminate a comparison signal voltage generated at the match line according to the comparison result of data. According to such memory array structure and operation, comparison operation can be performed at low power and at high speed while influence of search-line noise is avoided in a match line pair. Therefore, a low power content addressable memory which allows search operation at high speed can be realized.
摘要翻译： 在使用存储电路STC和比较器CP的存储器单元构成的存储器阵列中，将栅电极连接到搜索线的晶体管的源电极或漏电极的一个电极，构成 比较器CP连接到预充电到高电压的匹配线HMLr。 此外，匹配检测器MDr布置在预充电到低电压的匹配线LMLr上，以根据数据的比较结果来识别在匹配线处产生的比较信号电压。 根据这种存储器阵列结构和操作，可以在低功率和高速度下执行比较操作，同时在匹配线对中避免搜索线噪声的影响。 因此，可以实现允许高速搜索操作的低功率内容可寻址存储器。
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公开(公告)号：US07173838B2
公开(公告)日：2007-02-06
申请号：US11072246
申请日：2005-03-07
CPC分类号： G11C15/043 , G11C15/00
摘要： In accordance with the regions which are component elements of memory information (entry) and input information (comparison information or search key), quaternary information including a pair of the minimum value and the difference or ternary information including a pair of the data and the mask are used as I/O signals. In addition, in accordance with the two types of information, two types of encoding circuits and decoding circuits are disposed, and either one of the encoding circuits and the decoding circuits are activated in accordance with the values set to the registers disposed to designate the format of information in each region of the entry and the search key. By selecting the desired register from the plurality of registers in response to the external command signals and address signals, the encoding and decoding in accordance with the information to be processed are carried out.
摘要翻译： 根据作为存储器信息（输入）的组成要素的区域和输入信息（比较信息或搜索关键字），包括一对最小值和包含一对数据和掩模的差分或三元信息的四元信息 被用作I / O信号。 此外，根据两种类型的信息，设置两种类型的编码电路和解码电路，并且根据设置为指定格式的寄存器的值来激活编码电路和解码电路中的任一种 的条目和搜索关键字的每个区域中的信息。 通过响应于外部命令信号和地址信号从多个寄存器中选择所需的寄存器，执行根据要处理的信息的编码和解码。
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公开(公告)号：US20050270818A1
公开(公告)日：2005-12-08
申请号：US11072246
申请日：2005-03-07
IPC分类号： G11C15/04 , G11C15/00 , H04L12/701 , H04L12/741
CPC分类号： G11C15/043 , G11C15/00
摘要： In accordance with the regions which are component elements of memory information (entry) and input information (comparison information or search key), quaternary information including a pair of the minimum value and the difference or ternary information including a pair of the data and the mask are used as I/O signals. In addition, in accordance with the two types of information, two types of encoding circuits and decoding circuits are disposed, and either one of the encoding circuits and the decoding circuits are activated in accordance with the values set to the registers disposed to designate the format of information in each region of the entry and the search key. By selecting the desired register from the plurality of registers in response to the external command signals and address signals, the encoding and decoding in accordance with the information to be processed are carried out.
摘要翻译： 根据作为存储器信息（输入）的组成要素的区域和输入信息（比较信息或搜索关键字），包括一对最小值和包含一对数据和掩模的差分或三元信息的四元信息 被用作I / O信号。 此外，根据两种类型的信息，设置两种类型的编码电路和解码电路，并且根据设置为指定格式的寄存器的值来激活编码电路和解码电路中的任一种 的条目和搜索关键字的每个区域中的信息。 通过响应于外部命令信号和地址信号从多个寄存器中选择所需的寄存器，执行根据要处理的信息的编码和解码。
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公开(公告)号：US07505296B2
公开(公告)日：2009-03-17
申请号：US11877310
申请日：2007-10-23
IPC分类号： G11C15/00
CPC分类号： G11C15/04 , G11C15/043
摘要： The range-specified IP addresses are effectively stored to reduce the number of necessary entries thereby the memory capacity of TCAM is improved. The representative means of the present invention is that: the storage information (entry) and the input information (comparison information or search key) are the common block code such that any bit must be the logical value ‘1’; Match-lines are hierarchically structured and memory cells are arranged at the intersecting points of a plurality of sub-match lines and a plurality of search lines; Further the sub-match lines are connected to main-match lines through the sub-match detectors, respectively and main-match detectors are arranged on the main-match lines.
摘要翻译： 有效存储范围指定的IP地址，以减少必要条目的数量，从而提高TCAM的存储容量。 本发明的代表性手段是：存储信息（条目）和输入信息（比较信息或搜索关键字）是公共块码，使得任何位必须是逻辑值“1”; 匹配线是分层结构的，并且存储器单元被布置在多个子匹配线和多条搜索线的交叉点处; 此外，子匹配线分别通过子匹配检测器连接到主匹配线，并且主匹配检测器被布置在主匹配线上。
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公开(公告)号：US20100072451A1
公开(公告)日：2010-03-25
申请号：US12373185
申请日：2006-07-21
申请人： Motoyasu Terao , Satoru Hanzawa , Takahiro Morikawa , Kenzo Kurotsuchi , Riichiro Takemura , Norikatsu Takaura , Nozomu Matsuzaki
发明人： Motoyasu Terao , Satoru Hanzawa , Takahiro Morikawa , Kenzo Kurotsuchi , Riichiro Takemura , Norikatsu Takaura , Nozomu Matsuzaki
CPC分类号： G11C13/0004 , G11C2213/79 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625 , H01L45/1675
摘要： A recording layer 52 made of a chalcogenide material which stores a high-resistance state of a high electrical resistance value and a low-resistance state of a low electrical resistance value is used as a memory element RM in a memory cell region, and it is formed so that a concentration of Ga or In of a first layer 52a positioned on a lower electrode TP side of the recording layer 52 is higher than the corresponding concentration of a second layer 52b positioned on an upper electrode 53 side. For example, the recording layer is formed so that a content of Ga or In of the second layer is 5 atomic % or more smaller than that of the first layer. Also, a circuit which can reverse the voltage polarity between the upper electrode and the lower electrode in a set operation and a reset operation is provided.
摘要翻译： 作为存储单元区域中的存储元件RM，使用由存储高电阻值的高电阻状态和低电阻值的低电阻状态的硫族化物材料制成的记录层52， 使得位于记录层52的下电极TP侧的第一层52a中的Ga或In的浓度高于位于上电极53侧的第二层52b的相应浓度。 例如，记录层形成为使得第二层中的Ga或In的含量比第一层的含量低5原子％以上。 此外，提供了在设定操作和复位操作中可以反转上电极和下电极之间的电压极性的电路。
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