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    Semiconductor integrated circuit device
    1.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US07619911B2

    公开(公告)日：2009-11-17

    申请号：US10579911

    申请日：2003-11-21

    申请人： Satoru Hanzawa ,  Junji Shigeta ,  Shinichiro Kimura ,  Takeshi Sakata ,  Riichiro Takemura ,  Kazuhiko Kajigaya

    发明人： Satoru Hanzawa ,  Junji Shigeta ,  Shinichiro Kimura ,  Takeshi Sakata ,  Riichiro Takemura ,  Kazuhiko Kajigaya

    IPC分类号： G11C15/00

    CPC分类号： G11C15/04 ,  G11C15/043

    摘要： In a memory array structured of memory cells using a storage circuit STC and a comparator CP, either one electrode of a source electrode or a drain electrode of a transistor, whose gate electrode is connected to a search line, of a plurality of transistors structuring the comparator CP is connected to a match line HMLr precharged to a high voltage. Further, a match detector MDr is arranged on a match line LMLr precharged to a low voltage to discriminate a comparison signal voltage generated at the match line according to the comparison result of data. According to such memory array structure and operation, comparison operation can be performed at low power and at high speed while influence of search-line noise is avoided in a match line pair. Therefore, a low power content addressable memory which allows search operation at high speed can be realized.

    摘要翻译： 在使用存储电路STC和比较器CP的存储器单元构成的存储器阵列中，将栅电极连接到搜索线的晶体管的源电极或漏电极的一个电极，构成 比较器CP连接到预充电到高电压的匹配线HMLr。 此外，匹配检测器MDr布置在预充电到低电压的匹配线LMLr上，以根据数据的比较结果来识别在匹配线处产生的比较信号电压。 根据这种存储器阵列结构和操作，可以在低功率和高速度下执行比较操作，同时在匹配线对中避免搜索线噪声的影响。 因此，可以实现允许高速搜索操作的低功率内容可寻址存储器。

    Semiconductor Integrated Circuit Device
    2.
    发明申请
    Semiconductor Integrated Circuit Device 失效
    半导体集成电路器件

    公开(公告)号：US20070274144A1

    公开(公告)日：2007-11-29

    申请号：US10579911

    申请日：2003-11-21

    申请人： Satoru Hanzawa ,  Junji Shigeta ,  Shinichiro Kimura ,  Takeshi Sakata ,  Riichiro Takemura ,  Kazuhiko Kajigaya

    发明人： Satoru Hanzawa ,  Junji Shigeta ,  Shinichiro Kimura ,  Takeshi Sakata ,  Riichiro Takemura ,  Kazuhiko Kajigaya

    IPC分类号： G11C7/00

    CPC分类号： G11C15/04 ,  G11C15/043

    摘要： In a memory array structured of memory cells using a storage circuit STC and a comparator CP, either one electrode of a source electrode or a drain electrode of a transistor, whose gate electrode is connected to a search line, of a plurality of transistors structuring the comparator CP is connected to a match line HMLr precharged to a high voltage. Further, a match detector MDr is arranged on a match line LMLr precharged to a low voltage to discriminate a comparison signal voltage generated at the match line according to the comparison result of data. According to such memory array structure and operation, comparison operation can be performed at low power and at high speed while influence of search-line noise is avoided in a match line pair. Therefore, a low power content addressable memory which allows search operation at high speed can be realized.

    摘要翻译： 在使用存储电路STC和比较器CP的存储器单元构成的存储器阵列中，将栅电极连接到搜索线的晶体管的源电极或漏电极的一个电极，构成 比较器CP连接到预充电到高电压的匹配线HMLr。 此外，匹配检测器MDr布置在预充电到低电压的匹配线LMLr上，以根据数据的比较结果来识别在匹配线处产生的比较信号电压。 根据这种存储器阵列结构和操作，可以在低功率和高速度下执行比较操作，同时在匹配线对中避免搜索线噪声的影响。 因此，可以实现允许高速搜索操作的低功率内容可寻址存储器。

    Semiconductor integrated circuit device
    3.
    发明申请
    Semiconductor integrated circuit device 审中-公开
    半导体集成电路器件

    公开(公告)号：US20050035428A1

    公开(公告)日：2005-02-17

    申请号：US10946000

    申请日：2004-09-22

    申请人： Norikatsu Takaura ,  Riichiro Takemura ,  Hideyuki Matsuoka ,  Shinichiro Kimura ,  Hisao Asakura ,  Ryo Nagai ,  Satoru Yamada

    发明人： Norikatsu Takaura ,  Riichiro Takemura ,  Hideyuki Matsuoka ,  Shinichiro Kimura ,  Hisao Asakura ,  Ryo Nagai ,  Satoru Yamada

    IPC分类号： H01L21/76 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/08 ,  H01L27/092 ,  H01L27/105 ,  H01L27/108 ,  H01L29/76

    CPC分类号： H01L27/105 ,  H01L27/10897

    摘要： A semiconductor integrated circuit device is provided, in which variation in the threshold voltage of a MISFET, for example, a MISFET pair that constitute a sense amplifier, can be reduced. In a logic circuit area over which a logic circuit such as a sense amplifier circuit required to drive a memory cell is formed, n-type active areas having no gate electrode are arranged at both edges of active areas over which a p-channel MISFET pair for constituting a sense amplifier are formed. Assuming that the width between active areas nwp1 and nw1 is L4, the width between active areas nwp2 and nw2 is L6, and the width between active areas nwp1 and nwp2 is L5, (L4-L5), (L6-L5), and (L4-L6) are set equal to almost zero or smaller than twice the minimum processing dimension, so that the variation in shape of the device isolation trenches with the widths L4, L5, and L6 can be reduced, and the threshold voltage difference in the MISFET pair can be reduced.

    摘要翻译： 提供了一种半导体集成电路器件，其中可以减小MISFET的阈值电压的变化，例如构成读出放大器的MISFET对的变化。 在形成驱动存储单元所需的诸如读出放大器电路的逻辑电路的逻辑电路区域中，没有栅电极的n型有源区域被布置在有效区域的两个边缘上，p沟道MISFET对 用于构成读出放大器。 假设有效区域nwp1和nw1之间的宽度为L4，则有效区域nwp2和nw2之间的宽度为L6，有效区域nwp1和nwp2之间的宽度为L5（L4-L5），（L6-L5）和（ L4-L6）设定为几乎为零或小于最小加工尺寸的两倍，使得可以减小宽度L4，L5和L6的器件隔离沟槽形状的变化，并且可以减小阈值电压差 可以减少MISFET对。

    Semiconductor integrated circuit device
    5.
    发明授权
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US06812540B2

    公开(公告)日：2004-11-02

    申请号：US10298682

    申请日：2002-11-19

    申请人： Norikatsu Takaura ,  Riichiro Takemura ,  Hideyuki Matsuoka ,  Shinichiro Kimura ,  Hisao Asakura ,  Ryo Nagai ,  Satoru Yamada

    发明人： Norikatsu Takaura ,  Riichiro Takemura ,  Hideyuki Matsuoka ,  Shinichiro Kimura ,  Hisao Asakura ,  Ryo Nagai ,  Satoru Yamada

    IPC分类号： H01L2900

    CPC分类号： H01L27/105 ,  H01L27/10897

    摘要： A semiconductor integrated circuit device is provided, in which variation in the threshold voltage of a MISFET, for example, a MISFET pair that constitute a sense amplifier, can be reduced. In a logic circuit area over which a logic circuit such as a sense amplifier circuit required to drive a memory cell is formed, n-type active areas having no gate electrode are arranged at both edges of active areas over which a p-channel MISFET pair for constituting a sense amplifier are formed. Assuming that the width between active areas nwp1 and nw1 is L4, the width between active areas nwp2 and nw2 is L6, and the width between active areas nwp1 and nwp2 is L5, (L4−L5), (L6−L5), and (L4−L6) are set equal to almost zero or smaller than twice the minimum processing dimension, so that the variation in shape of the device isolation trenches with the widths L4, L5, and L6 can be reduced, and the threshold voltage difference in the MISFET pair can be reduced.

    摘要翻译： 提供了一种半导体集成电路器件，其中可以减小MISFET的阈值电压的变化，例如构成读出放大器的MISFET对的变化。 在形成驱动存储单元所需的诸如读出放大器电路的逻辑电路的逻辑电路区域中，没有栅电极的n型有源区域被布置在有效区域的两个边缘上，p沟道MISFET对 用于构成读出放大器。 假设有源区域nwp1和nw1之间的宽度为L4，有效区域nwp2和nw2之间的宽度为L6，有效区域nwp1和nwp2之间的宽度为L5（L4-L5），（L6-L5）和（ L4-L6）设定为几乎为零或小于最小加工尺寸的两倍，使得可以减小宽度L4，L5和L6的器件隔离沟槽形状的变化，并且可以减小阈值电压差 可以减少MISFET对。

    Semiconductor memory device and manufacturing method thereof
    8.
    发明授权
    Semiconductor memory device and manufacturing method thereof 有权
    半导体存储器件及其制造方法

    公开(公告)号：US06791134B2

    公开(公告)日：2004-09-14

    申请号：US10205421

    申请日：2002-07-26

    申请人： Shinichiro Kimura ,  Toshiaki Yamanaka ,  Kiyoo Itoh ,  Takeshi Sakata ,  Tomonori Sekiguchi ,  Hideyuki Matsuoka

    发明人： Shinichiro Kimura ,  Toshiaki Yamanaka ,  Kiyoo Itoh ,  Takeshi Sakata ,  Tomonori Sekiguchi ,  Hideyuki Matsuoka

    IPC分类号： H01L27108

    CPC分类号： H01L27/10852 ,  H01L27/108 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/90

    摘要： A capacitor consisting of a storage electrode (19), a capacitor dielectric film (20) and a plate electrode (21) is formed in a trench formed through dielectric films (6, 8, 10 and 12) stacked on a semiconductor substrate (1) and buried wiring layers (9 and 11) are formed under the capacitor. As the capacitor is formed not in the semiconductor substrate but over it, there is room in area in which the capacitor can be formed and the difficulty of forming wiring is reduced by using the wiring layers (9 and 11) for a global word line and a selector line. As the upper face of an dielectric film (32) which is in contact with the lower face of wiring (34) in a peripheral circuit area is extended into a memory cell area and is in contact with the side of the capacitor (33), step height between the peripheral circuit area and the memory cell area is remarkably reduced.

    摘要翻译： 在由半导体衬底（1）上层叠的电介质膜（6,8,10和12）形成的沟槽中形成由存储电极（19），电容器电介质膜（20）和平板电极（21）构成的电容器 ）和埋入布线层（9和11）形成在电容器下面。 由于电容器不是形成在半导体衬底中而是在其上形成，因此通过使用用于全局字线的布线层（9和11），可以形成电容器并且难以形成布线的难度减小， 随着在外围电路区域中与布线（34）的下表面接触的电介质膜（32）的上表面延伸到存储单元区域中并与电容器的侧面接触 （33），外围电路区域和存储单元区域之间的台阶高度显着降低。

    Semiconductor memory device and method of manufacturing the same
    10.
    发明授权
    Semiconductor memory device and method of manufacturing the same 失效
    半导体存储器件及其制造方法

    公开(公告)号：US06831316B1

    公开(公告)日：2004-12-14

    申请号：US10009826

    申请日：2002-03-19

    申请人： Hideyuki Matsuoka ,  Takeshi Sakata ,  Shinichiro Kimura ,  Toshiaki Yamanaka ,  Tsuyoshi Kachi ,  Tomonori Sekiguchi

    发明人： Hideyuki Matsuoka ,  Takeshi Sakata ,  Shinichiro Kimura ,  Toshiaki Yamanaka ,  Tsuyoshi Kachi ,  Tomonori Sekiguchi

    IPC分类号： H01L4700

    CPC分类号： H01L27/108 ,  H01L27/10894 ,  H01L27/10897

    摘要： An existent DRAM memory cell comprises transistors as a switch and capacitors for accumulating storage charges in which the height of the capacitor has been increased more and more along with micro miniaturization, which directly leads to increase in the manufacturing cost. The invention of the present application provides a semiconductor memory device of a basic constitution in which a memory cell array having plural memory cells disposed on a semiconductor substrate and word lines and data lines for selecting the memory cells and a peripheral circuit at the periphery of the memory cell array wherein the memory cell comprises a multi-layer of a conductive layer, an insulating layer and plural semiconductor layers containing impurities, and a potential can be applied to the insulating layer enabling the tunneling effect. The invention of the present application concerns a memory cell not requiring capacitor and capable of being formed in simple steps.

    摘要翻译： 存在的DRAM存储单元包括作为开关的晶体管和用于累积存储电荷的电容器，其中电容器的高度随着微型化而逐渐增加，这直接导致制造成本的增加。 本申请的发明提供了一种基本结构的半导体存储器件，其中具有设置在半导体衬底上的多个存储单元的存储单元阵列和用于选择存储单元的字线和数据线以及外围电路的外围电路 存储单元阵列，其中存储单元包括导电层的多层，绝缘层和含有杂质的多个半导体层，并且可以将电位施加到能够实现隧道效应的绝缘层。 本申请的发明涉及不需要电容器并能够以简单的步骤形成的存储单元。