公开(公告)号：US5937284A

公开(公告)日：1999-08-10

申请号：US979621

申请日：1997-11-28

申请人： Toshiaki Iwamatsu ,  Yasuo Inoue ,  Tadashi Nishimura

发明人： Toshiaki Iwamatsu ,  Yasuo Inoue ,  Tadashi Nishimura

IPC分类号： H01L27/12 ,  H01L21/00 ,  H01L21/425 ,  H01L21/76

CPC分类号： H01L27/1203

摘要： Generation of parasitic transistor in active layer edge is prevented. In an NMOS region of a semiconductor layer (21) on an insulating film (20), boron ions are implanted by rotary oblique injection, using a nitride film (23) and a resist (253a) as mask. In the vicinity of a region for separating element by LOCOS method, that is, only in the edge region of the semiconductor layer (21) as the active layer of NMOS transistor, boron ions are implanted by about 3.times.10.sup.13 /cm.sup.2. After LOCOS oxidation, the impurity concentration is heightened to such a level as the boron ions may not be sucked up into the oxide film.

摘要翻译： 防止有源层边缘中的寄生晶体管的产生。 在绝缘膜（20）上的半导体层（21）的NMOS区域中，使用氮化膜（23）和抗蚀剂（253a）作为掩模，通过旋转倾斜注入注入硼离子。 在通过LOCOS方法分离元件的区域附近，即仅在作为NMOS晶体管的有源层的半导体层（21）的边缘区域中，硼离子注入约3×10 13 / cm 2。 在LOCOS氧化之后，杂质浓度提高到这样的水平，因为硼离子可能不被吸入氧化膜中。

公开(公告)号：US5381235A

公开(公告)日：1995-01-10

申请号：US990460

申请日：1992-12-15

申请人： Yasuo Inoue ,  Tadashi Nishimura ,  Takashi Ipposhi ,  Toshiaki Iwamatsu

发明人： Yasuo Inoue ,  Tadashi Nishimura ,  Takashi Ipposhi ,  Toshiaki Iwamatsu

IPC分类号： G01B11/24 ,  G01B11/02 ,  G01B11/25 ,  G01C3/06 ,  H01L27/14

CPC分类号： G01B11/024 ,  G01B11/2518

摘要： The present invention provides a three-dimensional shape measuring device and a sensor employed for the three-dimensional shape measuring device. The three-dimensional shape measuring device comprises a light source for scanning plane light over the surface of an object, an image sensor opposed to the object and provided with a plurality of pixels, an optical system for forming an image of a bright line appearing on the surface of the object due to plane light on the image sensor, a plurality of capacitors installed in association with pixels of the image sensor, a charger for storing given charges in a plurality of capacitors before plane light scanning starts, a plurality of dischargers lying in association with capacitors and gradually discharging the capacitors for pixels corresponding to a bright line image from when plane light scanning starts until the bright line image passes through the pixels, and an arithmetic logic means for computing charges remaining in the plurality of capacitors after plane light scanning is completed and thus providing a three-dimensional shape of an object. Thereby, a three-dimensional shape of an object can be measured at a high speed with high precision.

摘要翻译： 本发明提供了三维形状测量装置和用于三维形状测量装置的传感器。 三维形状测量装置包括：用于扫描物体表面上的平面光的光源，与该物体相对并设置有多个像素的图像传感器，用于形成亮线的图像的光学系统， 由于图像传感器上的平面光，物体的表面，与图像传感器的像素相关联地安装的多个电容器，用于在平面光扫描开始之前在多个电容器中存储给定电荷的充电器，多个放电器位于 与平面光扫描开始直到亮线图像通过像素的与亮线图像相对应的像素的电容器逐渐放电;以及算术逻辑装置，用于计算平面光后的多个电容器中剩余的电荷 扫描完成，从而提供对象的三维形状。 由此，可以高精度地测量物体的三维形状。

公开(公告)号：US5619053A

公开(公告)日：1997-04-08

申请号：US454816

申请日：1995-05-31

申请人： Toshiaki Iwamatsu ,  Yasuo Inoue ,  Tadashi Nishimura

发明人： Toshiaki Iwamatsu ,  Yasuo Inoue ,  Tadashi Nishimura

IPC分类号： H01L27/12 ,  H01L27/01

CPC分类号： H01L27/1203

摘要： Generation of parasitic transistor in active layer edge is prevented, in an NMOS region of a semiconductor layer (21) on an insulating film (20), boron ions are implanted by rotary oblique injection, using a nitride film (23) and a resist (253a) as mask. In the vicinity of a region for separating element by LOCOS method, that is, only in the edge region of the semiconductor layer (21) as the active layer of NMOS transistor, boron ions are implanted by about 3.times.10.sup.13 /cm.sup.2. After LOCOS oxidation, the impurity concentration is heightened to such a level as the boron ions may not be sucked up into the oxide film.

摘要翻译： 在绝缘膜（20）上的半导体层（21）的NMOS区域中，通过旋转斜射注入硼离子，使用氮化物膜（23）和抗蚀剂（...）来防止在有源层边缘中产生寄生晶体管 253a）作为掩模。 在通过LOCOS方法分离元件的区域附近，即仅在作为NMOS晶体管的有源层的半导体层（21）的边缘区域中，硼离子注入约3×10 13 / cm 2。 在LOCOS氧化之后，杂质浓度提高到这样的水平，因为硼离子不能被吸入氧化膜中。

公开(公告)号：US6118154A

公开(公告)日：2000-09-12

申请号：US947345

申请日：1997-10-08

申请人： Yasuo Yamaguchi ,  Hirotoshi Sato ,  Yasuo Inoue ,  Toshiaki Iwamatsu

发明人： Yasuo Yamaguchi ,  Hirotoshi Sato ,  Yasuo Inoue ,  Toshiaki Iwamatsu

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L29/786 ,  H01L23/60

CPC分类号： H01L27/0251

摘要： An I/O protection circuit includes a P-channel MOS transistor connected between an input terminal and a power supply line, and an N-channel MOS transistor connected between the input terminal and a ground line. Gate electrodes of both the transistors are floated. The transistors may be replaced with gate diodes. Further, gate electrodes may be formed from the same layer as a gate electrode provided for field shielding.

摘要翻译： I / O保护电路包括连接在输入端和电源线之间的P沟道MOS晶体管和连接在输入端和接地线之间的N沟道MOS晶体管。 两个晶体管的栅极电极浮起来。 晶体管可以被栅极二极管代替。 此外，栅电极可以由与用于场屏蔽的栅电极相同的层形成。

公开(公告)号：US20060086934A1

公开(公告)日：2006-04-27

申请号：US11293171

申请日：2005-12-05

申请人： Toshiaki Iwamatsu ,  Yasuo Yamaguchi ,  Shigenobu Maeda ,  Shoichi Miyamoto ,  Akihiko Furukawa ,  Yasuo Inoue

发明人： Toshiaki Iwamatsu ,  Yasuo Yamaguchi ,  Shigenobu Maeda ,  Shoichi Miyamoto ,  Akihiko Furukawa ,  Yasuo Inoue

IPC分类号： H01L29/08 ,  H01L29/04 ,  H01L27/12 ,  H01L27/14

CPC分类号： H01L21/76297 ,  H01L21/26586 ,  H01L21/764 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78606 ,  H01L29/78612 ,  H01L29/78633 ,  H01L29/78654

摘要： In a semiconductor device having an SOI structure and a method of manufacturing the same, influence by a parasitic transistor can be prevented, and no disadvantage is caused in connection with a manufacturing process. In this semiconductor device, an upper side portion of a semiconductor layer is rounded. Thereby, concentration of an electric field at the upper side portion of the semiconductor layer can be prevented. As a result, lowering of a threshold voltage of a parasitic transistor can be prevented, so that the parasitic transistor does not adversely affect subthreshold characteristics of a regular transistor. Owing to provision of a concavity of a U-shaped section, generation of etching residue can be prevented when etching a gate electrode for patterning the same. Thereby, a disadvantage is not caused in connection with the manufacturing process.

公开(公告)号：US06509583B1

公开(公告)日：2003-01-21

申请号：US09677848

申请日：2000-10-03

申请人： Toshiaki Iwamatsu ,  Yasuo Yamaguchi ,  Shigenobu Maeda ,  Shoichi Miyamoto ,  Akihiko Furukawa ,  Yasuo Inoue

发明人： Toshiaki Iwamatsu ,  Yasuo Yamaguchi ,  Shigenobu Maeda ,  Shoichi Miyamoto ,  Akihiko Furukawa ,  Yasuo Inoue

IPC分类号： H01L2904

CPC分类号： H01L21/76297 ,  H01L21/26586 ,  H01L21/764 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78606 ,  H01L29/78612 ,  H01L29/78633 ,  H01L29/78654

摘要： In a semiconductor device having an SOI structure and a method of manufacturing the same, influence by a parasitic transistor can be prevented, and no disadvantage is caused in connection with a manufacturing process. In this semiconductor device, an upper side portion of a semiconductor layer is rounded. Thereby, concentration of an electric field at the upper side portion of the semiconductor layer can be prevented. As a result, lowering of a threshold voltage of a parasitic transistor can be prevented, so that the parasitic transistor does not adversely affect subthreshold characteristics of a regular transistor. Owing to provision of a concavity of a U-shaped section, generation of etching residue can be prevented when etching a gate electrode for patterning the same. Thereby, a disadvantage is not caused in connection with the manufacturing process.

公开(公告)号：US07001822B2

公开(公告)日：2006-02-21

申请号：US10682124

申请日：2003-10-10

申请人： Toshiaki Iwamatsu ,  Yasuo Yamaguchi ,  Shigenobu Maeda ,  Shoichi Miyamoto ,  Akihiko Furukawa ,  Yasuo Inoue

发明人： Toshiaki Iwamatsu ,  Yasuo Yamaguchi ,  Shigenobu Maeda ,  Shoichi Miyamoto ,  Akihiko Furukawa ,  Yasuo Inoue

IPC分类号： H01L21/76

CPC分类号： H01L21/76297 ,  H01L21/26586 ,  H01L21/764 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78606 ,  H01L29/78612 ,  H01L29/78633 ,  H01L29/78654

摘要： In a semiconductor device having an SOI structure and a method of manufacturing the same, influence by a parasitic transistor can be prevented, and no disadvantage is caused in connection with a manufacturing process. In this semiconductor device, an upper side portion of a semiconductor layer is rounded. Thereby, concentration of an electric field at the upper side portion of the semiconductor layer can be prevented. As a result, lowering of a threshold voltage of a parasitic transistor can be prevented, so that the parasitic transistor does not adversely affect subthreshold characteristics of a regular transistor. Owing to provision of a concavity of a U-shaped section, generation of etching residue can be prevented when etching a gate electrode for patterning the same. Thereby, a disadvantage is not caused in connection with the manufacturing process.

公开(公告)号：US06653656B2

公开(公告)日：2003-11-25

申请号：US10336758

申请日：2003-01-06

申请人： Toshiaki Iwamatsu ,  Yasuo Yamaguchi ,  Shigenobu Maeda ,  Shoichi Miyamoto ,  Akihiko Furukawa ,  Yasuo Inoue

发明人： Toshiaki Iwamatsu ,  Yasuo Yamaguchi ,  Shigenobu Maeda ,  Shoichi Miyamoto ,  Akihiko Furukawa ,  Yasuo Inoue

IPC分类号： H01L2904

CPC分类号： H01L21/76297 ,  H01L21/26586 ,  H01L21/764 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78606 ,  H01L29/78612 ,  H01L29/78633 ,  H01L29/78654

摘要： In a semiconductor device having an SOI structure and a method of manufacturing the same, influence by a parasitic transistor can be prevented, and no disadvantage is caused in connection with a manufacturing process. In this semiconductor device, an upper side portion of a semiconductor layer is rounded. Thereby, concentration of an electric field at the upper side portion of the semiconductor layer can be prevented. As a result, lowering of a threshold voltage of a parasitic transistor can be prevented, so that the parasitic transistor does not adversely affect subthreshold characteristics of a regular transistor. Owing to provision of a concavity of a U-shaped section, generation of etching residue can be prevented when etching a gate electrode for patterning the same. Thereby, a disadvantage is not caused in connection with the manufacturing process.

摘要翻译： 在具有SOI结构的半导体器件及其制造方法中，可以防止寄生晶体管的影响，并且与制造过程相关的缺点不会产生。 在该半导体器件中，半导体层的上侧部分是圆形的。 由此，可以防止半导体层的上侧部分的电场集中。 结果，可以防止寄生晶体管的阈值电压的降低，使得寄生晶体管不会对正常晶体管的亚阈值特性产生不利影响。 通过设置U形截面的凹部，当蚀刻用于图案化的栅电极时，可以防止产生蚀刻残留。 因此，不会在制造过程中引起缺点。

公开(公告)号：US6144072A

公开(公告)日：2000-11-07

申请号：US231548

申请日：1999-01-15

申请人： Toshiaki Iwamatsu ,  Yasuo Yamaguchi ,  Shigenobu Maeda ,  Shoichi Miyamoto ,  Akihiko Furukawa ,  Yasuo Inoue

发明人： Toshiaki Iwamatsu ,  Yasuo Yamaguchi ,  Shigenobu Maeda ,  Shoichi Miyamoto ,  Akihiko Furukawa ,  Yasuo Inoue

IPC分类号： H01L21/764 ,  H01L21/265 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L27/01

CPC分类号： H01L21/76297 ,  H01L21/764 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78606 ,  H01L29/78612 ,  H01L29/78633 ,  H01L29/78654 ,  H01L21/26586

摘要： In a semiconductor device having an SOI structure and a method of manufacturing the same, influence by a parasitic transistor can be prevented, and no disadvantage is caused in connection with a manufacturing process. In this semiconductor device, an upper side portion of a semiconductor layer is rounded. Thereby, concentration of an electric field at the upper side portion of the semiconductor layer can be prevented. As a result, lowering of a threshold voltage of a parasitic transistor can be prevented, so that the parasitic transistor does not adversely affect subthreshold characteristics of a regular transistor. Owing to provision of a concavity of a U-shaped section, generation of etching residue can be prevented when etching a gate electrode for patterning the same. Thereby, a disadvantage is not caused in connection with the manufacturing process.

公开(公告)号：US5905286A

公开(公告)日：1999-05-18

申请号：US794504

申请日：1997-02-04

申请人： Toshiaki Iwamatsu ,  Yasuo Yamaguchi ,  Shigenobu Maeda ,  Shoichi Miyamoto ,  Akihiko Furukawa ,  Yasuo Inoue

发明人： Toshiaki Iwamatsu ,  Yasuo Yamaguchi ,  Shigenobu Maeda ,  Shoichi Miyamoto ,  Akihiko Furukawa ,  Yasuo Inoue

IPC分类号： H01L21/764 ,  H01L21/265 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L27/01 ,  H01L31/0392

CPC分类号： H01L21/76297 ,  H01L21/764 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78606 ,  H01L29/78612 ,  H01L29/78633 ,  H01L29/78654 ,  H01L21/26586

摘要： In a semiconductor device having an SOI structure and a method of manufacturing the same, influence by a parasitic transistor can be prevented, and no disadvantage is caused in connection with a manufacturing process. In this semiconductor device, an upper side portion of a semiconductor layer is rounded. Thereby, concentration of an electric field at the upper side portion of the semiconductor layer can be prevented. As a result, lowering of a threshold voltage of a parasitic transistor can be prevented, so that the parasitic transistor does not adversely affect subthreshold characteristics of a regular transistor. Owing to provision of a concavity of a U-shaped section, generation of etching residue can be prevented when etching a gate electrode for patterning the same. Thereby, a disadvantage is not caused in connection with the manufacturing process.

摘要翻译： 在具有SOI结构的半导体器件及其制造方法中，可以防止寄生晶体管的影响，并且与制造过程相关的缺点不会产生。 在该半导体器件中，半导体层的上侧部分是圆形的。 由此，可以防止半导体层的上侧部分的电场集中。 结果，可以防止寄生晶体管的阈值电压的降低，使得寄生晶体管不会对正常晶体管的亚阈值特性产生不利影响。 通过设置U形截面的凹部，当蚀刻用于图案化的栅电极时，可以防止产生蚀刻残留。 因此，不会在制造过程中引起缺点。