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    Semiconductor device
    11.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US06492672B1

    公开(公告)日：2002-12-10

    申请号：US09629861

    申请日：2000-08-01

    申请人： Mizuki Segawa ,  Toshiki Yabu ,  Takashi Uehara ,  Takashi Nakabayashi ,  Kyoji Yamashita ,  Takaaki Ukeda ,  Masatoshi Arai ,  Takayuki Yamada

    发明人： Mizuki Segawa ,  Toshiki Yabu ,  Takashi Uehara ,  Takashi Nakabayashi ,  Kyoji Yamashita ,  Takaaki Ukeda ,  Masatoshi Arai ,  Takayuki Yamada

    IPC分类号： H01L27108

    CPC分类号： H01L27/11526 ,  H01L21/82345 ,  H01L27/0629 ,  H01L27/105 ,  H01L27/11543 ,  H01L28/40 ,  Y10S438/957

    摘要： A MOS transistor includes a gate oxide film, and a gate electrode which is formed by a lamination of first and second conductor films. A capacitive element includes a lower capacitive electrode formed of the first conductor film, a capacitive film made of an insulating film which is different from the gate oxide film, an upper capacitive electrode formed of the second conductor film on the capacitive film, and a leading electrode of the lower capacitive electrode formed of the second conductor film. At the same number of steps as in the case where the gate oxide film is used as the capacitive film, a semiconductor device can be manufactured with the capacitive film provided, the capacitive film being made of a nitride film or the like that is different from the gate oxide film. Consequently, a capacitive film having a great capacitance value per unit area is used so that the occupied area can be reduced and an increase in manufacturing cost can be controlled. In the semiconductor device in which a transistor, a capacitive element, a resistive film and the like are provided, the occupied area can be reduced and the manufacturing cost can be cut down.

    摘要翻译： MOS晶体管包括栅极氧化膜和通过第一和第二导体膜的叠层形成的栅电极。 电容元件包括由第一导体膜形成的下部电容电极，由与栅极氧化膜不同的绝缘膜制成的电容膜，由电容膜上的第二导体膜形成的上部电容电极，以及引线 电极由第二导电膜形成。 以与使用栅极氧化膜作为电容膜的情况相同的步骤，可以制造具有设置的电容膜的半导体器件，电容膜由与氮化物膜不同的氮化物膜等构成 栅氧化膜。 因此，使用具有每单位面积的大的电容值的电容膜，从而可以减小占用面积并且可以控制制造成本的增加。 在其中提供晶体管，电容元件，电阻膜等的半导体器件中，可以减小占用面积并且可以减少制造成本。

    Semiconductor device which reduces the minimum distance requirements between active areas
    12.
    发明授权
    Semiconductor device which reduces the minimum distance requirements between active areas 失效
    降低有效区域之间最小距离要求的半导体器件

    公开(公告)号：US06281562B1

    公开(公告)日：2001-08-28

    申请号：US08685726

    申请日：1996-07-24

    申请人： Mizuki Segawa ,  Isao Miyanaga ,  Toshiki Yabu ,  Takashi Nakabayashi ,  Takashi Uehara ,  Kyoji Yamashita ,  Takaaki Ukeda ,  Masatoshi Arai ,  Takayuki Yamada ,  Michikazu Matsumoto

    发明人： Mizuki Segawa ,  Isao Miyanaga ,  Toshiki Yabu ,  Takashi Nakabayashi ,  Takashi Uehara ,  Kyoji Yamashita ,  Takaaki Ukeda ,  Masatoshi Arai ,  Takayuki Yamada ,  Michikazu Matsumoto

    IPC分类号： H01L29167

    CPC分类号： H01L29/6659 ,  H01L21/76224 ,  H01L29/665 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area. In this manner, the integration of a semiconductor device can be improved and an area occupied by the semiconductor device can be decreased without causing degradation of junction voltage resistance and increase of a junction leakage current in the semiconductor device.

    摘要翻译： 形成了比硅衬底的有源区域更高级的隔离。 在有源区域上，形成包括栅极氧化膜，栅电极，栅极保护膜，侧壁等的FET。 绝缘膜沉积在基板的整个顶表面上，并且在绝缘膜上形成用于暴露在有源区上延伸的区域，一部分隔离栅极保护膜的抗蚀剂膜。 不需要提供用于避免与形成连接孔的区域的隔离等的干涉的取向余量。 由于隔离比有源区域以逐步方式更高，所以通过在形成连接孔中的过度蚀刻来防止隔离物与有源区域中的杂质浓度低的部分接触。 以这种方式，可以改善半导体器件的集成，并且可以降低半导体器件占据的面积，而不会导致半导体器件中的结电阻的劣化和结漏电流的增加。

    Method of manufacturing semiconductor device
    13.
    发明授权
    Method of manufacturing semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US5960300A

    公开(公告)日：1999-09-28

    申请号：US574690

    申请日：1995-12-19

    申请人： Toshiki Yabu ,  Takashi Uehara ,  Mizuki Segawa ,  Takashi Nakabayashi

    发明人： Toshiki Yabu ,  Takashi Uehara ,  Mizuki Segawa ,  Takashi Nakabayashi

    IPC分类号： H01L21/762 ,  H01L21/76

    CPC分类号： H01L21/76229

    摘要： On a semiconductor substrate are successively deposited a silicon dioxide film and a silicon nitride film. The silicon nitride film, the silicon dioxide film, and the semiconductor substrate are sequentially etched using a photoresist film with an opening corresponding to an isolation region, thereby forming a trench. After depositing a diffusion preventing film, there is deposited an insulating film for isolation having reflowability. Although a void is formed in the insulating film for isolation in the isolation region, the insulating film for isolation is caused to reflow, thereby eliminating the void. After that, the whole substrate is planarized by CMP so as to remove the silicon nitride film and the silicon dioxide film, followed by the formation of gate insulating films, gate electrodes, sidewalls, and source/drain regions in respective element formation regions. Thus, in a highly integrated semiconductor device having a trench isolation, degradation of reliability resulting from the opening of the void in the surface of isolation is prevented.

    摘要翻译： 在半导体衬底上依次沉积二氧化硅膜和氮化硅膜。 使用具有对应于隔离区域的开口的光致抗蚀剂膜，依次蚀刻氮化硅膜，二氧化硅膜和半导体衬底，从而形成沟槽。 在沉积防扩散膜之后，沉积具有可回流性的用于隔离的绝缘膜。 虽然在隔离区域中用于隔离的绝缘膜中形成空隙，但是使用于隔离的绝缘膜回流，从而消除空隙。 之后，通过CMP对整个基板进行平坦化，以除去氮化硅膜和二氧化硅膜，然后在各个元件形成区域中形成栅极绝缘膜，栅极电极，侧壁和源极/漏极区域。 因此，在具有沟槽隔离的高度集成的半导体器件中，防止了由于隔离表面中的空隙的打开引起的可靠性降低。

    Semiconductor device and method of manufacturing the same
    14.
    发明授权
    Semiconductor device and method of manufacturing the same 失效
    半导体装置及其制造方法

    公开(公告)号：US5946563A

    公开(公告)日：1999-08-31

    申请号：US880880

    申请日：1997-06-23

    申请人： Takashi Uehara ,  Toshiki Yabu ,  Mizuki Segawa ,  Takashi Nakabayashi ,  Minoru Fujii

    发明人： Takashi Uehara ,  Toshiki Yabu ,  Mizuki Segawa ,  Takashi Nakabayashi ,  Minoru Fujii

    IPC分类号： H01L21/336 ,  H01L23/485 ,  H01L29/423 ,  H01L29/78 ,  H01L21/338

    CPC分类号： H01L29/6659 ,  H01L21/76895 ,  H01L23/485 ,  H01L29/42376 ,  H01L29/7833 ,  H01L2924/0002 ,  Y10S438/926

    摘要： There are provided: an isolation protruding upward from a semiconductor substrate in an active region; a gate electrode formed in the active region; and a pair of dummy electrodes formed to extend over the active region and the isolation and substantially in parallel with the gate electrode. Each of the gate electrode and dummy electrodes is composed of a lower film and an upper film. The lower films of the dummy electrodes are formed flush with the isolation and in contact with the side edges of the isolation. With the dummy electrodes, any gate electrode can be formed in a line-and-space pattern, so that the finished sizes of the gate electrode become uniform. This enables a reduction in gate length and therefore provides a semiconductor device of higher integration which is operable at a higher speed and substantially free from variations in finished size resulting from the use of different gate patterns.

    摘要翻译： 提供：在有源区域中从半导体衬底向上突出的隔离件; 形成在有源区中的栅电极; 以及一对虚拟电极，其形成为在有源区域上延伸并且隔离并且基本上与栅电极平行。 栅电极和虚拟电极各自由下膜和上膜构成。 虚拟电极的下部薄膜与隔离件的侧边缘隔离形成平齐的表面。 利用虚拟电极，可以以线间距图案形成任何栅电极，使得栅电极的成品尺寸变得均匀。 这使得能够减小栅极长度并因此提供更高集成度的半导体器件，该半导体器件可以以更高的速度操作，并且基本上不受使用不同栅极图案造成的成品尺寸的变化。

    Manufacturing method of CMOS transistor
    17.
    发明授权
    Manufacturing method of CMOS transistor 失效
    CMOS晶体管的制造方法

    公开(公告)号：US5756382A

    公开(公告)日：1998-05-26

    申请号：US784354

    申请日：1997-01-23

    申请人： Mizuki Segawa ,  Yoshiaki Kato ,  Hiroaki Nakaoka ,  Takashi Nakabayashi ,  Atsushi Hori ,  Hiroshi Masuda ,  Ichiro Matsuo ,  Akihira Shinohara ,  Takashi Uehara ,  Mitsuo Yasuhira

    发明人： Mizuki Segawa ,  Yoshiaki Kato ,  Hiroaki Nakaoka ,  Takashi Nakabayashi ,  Atsushi Hori ,  Hiroshi Masuda ,  Ichiro Matsuo ,  Akihira Shinohara ,  Takashi Uehara ,  Mitsuo Yasuhira

    IPC分类号： H01L21/8238 ,  H01L21/265

    CPC分类号： H01L21/823814 ,  Y10S148/147

    摘要： Gate electrodes of an N-channel transistor and a P-channel transistor are formed on a semiconductor substrate with a gate insulator therebetween. After conducting a first thermal treatment to the gate electrodes, N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor are formed using the gate electrode of the N-channel transistor as a mask. After conducting a second thermal treatment to the N-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment, P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor are formed using the gate electrode of the P-channel transistor as a mask. Then, a third thermal treatment is conducted to the P-type heavily doped diffusion layers at a lower temperature than that of the second thermal treatment.

    摘要翻译： N沟道晶体管和P沟道晶体管的栅电极形成在半导体衬底上，栅极绝缘体在其间。 在对栅电极进行第一热处理之后，使用N沟道晶体管的栅电极作为掩模来形成作为N沟道晶体管的源极或漏极的N型重掺杂扩散层。 在比第一热处理的温度低的情况下对N型重掺杂扩散层进行第二次热处理之后，使用P型重掺杂扩散层作为P沟道晶体管的源极或漏极，形成为使用 P沟道晶体管的栅电极作为掩模。 然后，在比第二热处理的温度低的温度下对P型重掺杂扩散层进行第三次热处理。

    Manufacturing method of CMOS transistor
    18.
    发明授权
    Manufacturing method of CMOS transistor 失效
    CMOS晶体管的制造方法

    公开(公告)号：US5726071A

    公开(公告)日：1998-03-10

    申请号：US789315

    申请日：1997-01-23

    申请人： Mizuki Segawa ,  Yoshiaki Kato ,  Hiroaki Nakaoka ,  Takashi Nakabayashi ,  Atsushi Hori ,  Hiroshi Masuda ,  Ichiro Matsuo ,  Akihira Shinohara ,  Takashi Uehara ,  Mitsuo Yasuhira

    发明人： Mizuki Segawa ,  Yoshiaki Kato ,  Hiroaki Nakaoka ,  Takashi Nakabayashi ,  Atsushi Hori ,  Hiroshi Masuda ,  Ichiro Matsuo ,  Akihira Shinohara ,  Takashi Uehara ,  Mitsuo Yasuhira

    IPC分类号： H01L21/8238 ,  H01L21/70

    CPC分类号： H01L21/823814 ,  Y10S148/147

    摘要： Gate electrodes of an N-channel transistor and a P-channel transistor are formed on a semiconductor substrate with a gate insulator therebetween. After conducting a first thermal treatment to the gate electrodes, N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor are formed using the gate electrode of the N-channel transistor as a mask. After conducting a second thermal treatment to the N-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment. P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor are formed using the gate electrode of the P-channel transistor as a mask. Then, a third thermal treatment is conducted to the P-type heavily doped diffusion layers at a lower temperature than that of the second thermal treatment.

    摘要翻译： N沟道晶体管和P沟道晶体管的栅电极形成在半导体衬底上，栅极绝缘体在其间。 在对栅电极进行第一热处理之后，使用N沟道晶体管的栅电极作为掩模来形成作为N沟道晶体管的源极或漏极的N型重掺杂扩散层。 在比第一热处理的温度低的温度下对N型重掺杂扩散层进行第二次热处理。 使用P沟道晶体管的栅电极作为掩模来形成作为P沟道晶体管的源极或漏极的P型重掺杂扩散层。 然后，在比第二热处理的温度低的温度下对P型重掺杂扩散层进行第三次热处理。

    Manufacturing method of CMOS transistor
    19.
    发明授权
    Manufacturing method of CMOS transistor 失效
    CMOS晶体管的制造方法

    公开(公告)号：US5686340A

    公开(公告)日：1997-11-11

    申请号：US723710

    申请日：1996-09-30

    申请人： Mizuki Segawa ,  Yoshiaki Kato ,  Hiroaki Nakaoka ,  Takashi Nakabayashi ,  Atsushi Hori ,  Hiroshi Masuda ,  Ichiro Matsuo ,  Akihira Shinohara ,  Takashi Uehara ,  Mitsuo Yasuhira

    发明人： Mizuki Segawa ,  Yoshiaki Kato ,  Hiroaki Nakaoka ,  Takashi Nakabayashi ,  Atsushi Hori ,  Hiroshi Masuda ,  Ichiro Matsuo ,  Akihira Shinohara ,  Takashi Uehara ,  Mitsuo Yasuhira

    IPC分类号： H01L21/8238 ,  H01L21/265

    CPC分类号： H01L21/823814 ,  Y10S148/147

    摘要： Gate electrodes of an N-channel transistor and a P-channel transistor are formed on a semiconductor substrate with a gate insulator therebetween. After conducting a first thermal treatment to the gate electrodes, N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor are formed using the gate electrode of the N-channel transistor as a mask. After conducting a second thermal treatment to the N-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment. P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor are formed using the gate electrode of the P-channel transistor as a mask. Then, a third thermal treatment is conducted to the P-type heavily doped diffusion layers at a lower temperature than that of the second thermal treatment.

    摘要翻译： N沟道晶体管和P沟道晶体管的栅电极形成在半导体衬底上，栅极绝缘体在其间。 在对栅电极进行第一热处理之后，使用N沟道晶体管的栅电极作为掩模来形成作为N沟道晶体管的源极或漏极的N型重掺杂扩散层。 在比第一热处理的温度低的温度下对N型重掺杂扩散层进行第二次热处理。 使用P沟道晶体管的栅电极作为掩模来形成作为P沟道晶体管的源极或漏极的P型重掺杂扩散层。 然后，在比第二热处理的温度低的温度下对P型重掺杂扩散层进行第三次热处理。