公开(公告)号：US06917073B2

公开(公告)日：2005-07-12

申请号：US10643877

申请日：2003-08-20

申请人： Mu-Yi Liu ,  Chih-Chieh Yeh ,  Tso-Hung Fan ,  Tao-Cheng Lu

发明人： Mu-Yi Liu ,  Chih-Chieh Yeh ,  Tso-Hung Fan ,  Tao-Cheng Lu

IPC分类号： H01L27/115 ,  H01L29/792

CPC分类号： H01L29/792 ,  H01L27/115

摘要： To reduce the disturbance between adjacent memory cells, an improved ONO flash memory array is implanted with a pocket on one side of the channel of each memory cell or two pockets of different concentrations on both sides of the channel, thereby resulting in memory cells with asymmetric pockets. Consequently, no disturbances occurred between adjacent memory cells when the ONO flash memory array is programmed or erased by band-to-band techniques, and the disturbances between adjacent memory cells are also suppressed during reading process.

摘要翻译： 为了减少相邻存储单元之间的干扰，改进的ONO闪速存储器阵列在通道两侧的每个存储单元的通道的一侧或两个不同浓度的凹槽的一侧上注入一个口袋，从而导致不对称的存储单元 口袋 因此，当通过频带技术对ONO闪速存储器阵列进行编程或擦除时，相邻存储单元之间不会发生干扰，并且在读取过程中相邻存储单元之间的干扰也被抑制。

公开(公告)号：US20050040458A1

公开(公告)日：2005-02-24

申请号：US10643877

申请日：2003-08-20

申请人： Mu-Yi Liu ,  Chih-Chieh Yeh ,  Tso-Hung Fan ,  Tao-Cheng Lu

发明人： Mu-Yi Liu ,  Chih-Chieh Yeh ,  Tso-Hung Fan ,  Tao-Cheng Lu

IPC分类号： H01L27/115 ,  H01L29/792

CPC分类号： H01L29/792 ,  H01L27/115

摘要： To reduce the disturbance between adjacent memory cells, an improved ONO flash memory array is implanted with a pocket on one side of the channel of each memory cell or two pockets of different concentrations on both sides of the channel, thereby resulting in memory cells with asymmetric pockets. Consequently, no disturbances occurred between adjacent memory cells when the ONO flash memory array is programmed or erased by band-to-band techniques, and the disturbances between adjacent memory cells are also suppressed during reading process.

摘要翻译： 为了减少相邻存储单元之间的干扰，改进的ONO闪速存储器阵列在通道两侧的每个存储单元的通道的一侧或两个不同浓度的凹槽的一侧上注入一个口袋，从而导致不对称的存储单元 口袋 因此，当通过频带技术对ONO闪速存储器阵列进行编程或擦除时，相邻存储单元之间不会发生干扰，并且在读取过程中相邻存储单元之间的干扰也被抑制。

公开(公告)号：US06687160B1

公开(公告)日：2004-02-03

申请号：US10064918

申请日：2002-08-29

申请人： Tso-Hung Fan ,  Chih-Chieh Yeh ,  Tao-Cheng Lu

发明人： Tso-Hung Fan ,  Chih-Chieh Yeh ,  Tao-Cheng Lu

IPC分类号： G11C1606

CPC分类号： G11C16/12 ,  G11C5/147 ,  G11C11/5621 ,  G11C11/5642 ,  G11C2211/5634

摘要： A reference current generation circuit for the multiple bit flash memory provided by the present invention applies the same boosted word-line voltage to the gates of different reference current generation unit's reference cells, and uses different gate lengths from different reference cells to obtain the reference currents with different levels that are needed. Therefore, it effectively solves the problem of the reference currents having different drifts along with the variance of the temperature and the power voltage Vcc.

摘要翻译： 本发明提供的用于多位闪速存储器的参考电流产生电路将相同的升压字线电压施加到不同参考电流产生单元的参考单元的栅极，并且使用来自不同参考单元的不同栅极长度来获得参考电流 需要不同的水平。 因此，它有效地解决了具有不同漂移的参考电流以及温度变化和电源电压Vcc的问题。

公开(公告)号：US06587387B1

公开(公告)日：2003-07-01

申请号：US10055571

申请日：2002-01-22

申请人： Tso-Hung Fan ,  Yen-Hung Yeh ,  Kwang-Yang Chan ,  Mu-Yi Liu ,  Tao-Cheng Lu

发明人： Tso-Hung Fan ,  Yen-Hung Yeh ,  Kwang-Yang Chan ,  Mu-Yi Liu ,  Tao-Cheng Lu

IPC分类号： G11C2900

CPC分类号： G11C29/025 ,  G11C17/14 ,  G11C29/02 ,  G11C2029/5006

摘要： A Mask ROM testing device is described. The Mask ROM testing device comprises a substrate, a plurality of buried bit-lines in the substrate and a plurality of word-lines on the substrate perpendicular to the buried bit-lines. Each buried bit-line has two end portions with a combined length of about 3˜30 &mgr;m and can have an N-type conductivity or a P-type conductivity.

摘要翻译： 描述了面罩ROM测试装置。 掩模ROM测试装置包括衬底，衬底中的多个掩埋位线和垂直于掩埋位线的衬底上的多个字线。 每个埋置的位线具有两个具有约3〜30μm的组合长度的端部，并且可以具有N型导电性或P型导电性。

公开(公告)号：US06958934B2

公开(公告)日：2005-10-25

申请号：US10065761

申请日：2002-11-15

申请人： Tso-Hung Fan ,  Chih-Chieh Yeh ,  Tao-Cheng Lu

发明人： Tso-Hung Fan ,  Chih-Chieh Yeh ,  Tao-Cheng Lu

IPC分类号： G11C11/56 ,  G11C16/02

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C11/5635 ,  G11C2211/5621

摘要： A programming method of the multi-level flash memory comprises shooting a programming voltage that is increasing upwards stepwise each time into the gate of the multi-level flash memory, and following, shooting a program verify voltage that is decreasing downwards to program a multi-level in the multi-level flash memory and shooting an additional programming voltage into the multi-level flash memory after the last program verify voltage is shot. An erasing method of the multi-level flash memory comprises shooting an erasing voltage that is decreasing downwards stepwise each time into a gate of the multi-level flash memory, and following, shooting a erase verify voltage that is increasing upwards to erase a multi-level in the multi-level flash memory and shooting an additional voltage into the multi-level flash memory after the last erase verify voltage is shot.

摘要翻译： 多级闪存的编程方法包括拍摄每次逐步向多级闪速存储器的门逐渐增加的编程电压，并且随后，拍摄向下减小的编程验证电压， 在最后一个程序验证电压被拍摄之后，在多级闪存中高电平并在多级闪存中拍摄附加的编程电压。 多级闪速存储器的擦除方法包括拍摄每次逐步向下逐渐减小到多级闪存的门的擦除电压，随后，拍摄向上增加的擦除验证电压以擦除多级闪存， 在最后擦除验证电压被拍摄之后，多级闪存中的电平和多级闪存中的附加电压。

公开(公告)号：US06838691B2

公开(公告)日：2005-01-04

申请号：US10090542

申请日：2002-03-04

申请人： Mu-Yi Liu ,  Tso-Hung Fan ,  Kwang-Yang Chan ,  Yen-Hung Yeh ,  Tao-Cheng Lu

发明人： Mu-Yi Liu ,  Tso-Hung Fan ,  Kwang-Yang Chan ,  Yen-Hung Yeh ,  Tao-Cheng Lu

IPC分类号： H01L27/24 ,  H01L29/04 ,  H01L29/06

CPC分类号： H01L27/24

摘要： A method of manufacturing chalcogenide memory in a semiconductor substrate. The method includes the steps of forming a N+ epitaxy layer on the semiconductor substrate; forming a N− epitaxy layer on the N+ epitaxy layer; forming a first STI in the N+ and N− epitaxy layers to isolate a predetermined word line region; forming a second STI in the N− epitaxy layer to isolate a predetermined P+ doped region; forming a dielectric layer on the N− epitaxy layer; patterning the dielectric layer to form a first opening and performing a N+ doping on the N− epitaxy layer via the first opening such that a N+ doped region is formed in the N− epitaxy layer and connected to the N+ epitaxy layer; patterning the dielectric layer to form a second opening and performing a P+ doping on the N− epitaxy layer such that a P+ doped region is formed; forming contact plugs in the first opening and the second opening respectively; and forming an electrode on each contact plug, wherein the electrode includes a lower electrode, a chalcogenide layer and an upper electrode.

摘要翻译： 在半导体衬底中制造硫族化物存储器的方法。 该方法包括在半导体衬底上形成N +外延层的步骤; 在N +外延层上形成N-外延层; 在N +和N-外延层中形成第一STI以隔离预定的字线区域; 在所述N-外延层中形成第二STI以隔离预定的P +掺杂区; 在所述N-外延层上形成介电层; 图案化介电层以形成第一开口，并且经由第一开口在N外延层上进行N +掺杂，使得N +掺杂区形成在N外延层中并连接到N +外延层; 图案化介电层以形成第二开口并且在N外延层上执行P +掺杂以形成P +掺杂区域; 分别在所述第一开口和所述第二开口中形成接触塞; 以及在每个接触塞上形成电极，其中所述电极包括下电极，硫族化物层和上电极。

公开(公告)号：US06834013B2

公开(公告)日：2004-12-21

申请号：US10015414

申请日：2001-12-12

申请人： Tso-Hung Fan ,  Yen-Hung Yeh ,  Kwang-Yang Chan ,  Mu-Yi Liu ,  Tao-Cheng Lu

发明人： Tso-Hung Fan ,  Yen-Hung Yeh ,  Kwang-Yang Chan ,  Mu-Yi Liu ,  Tao-Cheng Lu

IPC分类号： G11C1604

CPC分类号： G11C16/0466 ,  G11C16/10 ,  G11C16/14

摘要： A method for programming and erasing a non-volatile memory with a nitride tunneling layer is described. The non-volatile memory is programmed by applying a first voltage to the gate and grounding the substrate to turn on a channel between the source and the drain, and applying a second voltage to the drain and grounding the source to induce a current in the channel and thereby to generate hot electrons therein. The hot electrons are injected into a charge-trapping layer of the non-volatile and trapped therein through the nitride tunneling layer. The non-volatile memory is erased by applying a first positive bias to the drain, applying a second positive bias to the gate, and grounding the source and the substrate to generate hot electron holes in the channel region. The hot electron holes are injected into the charge-trapping layer through the nitride tunneling layer.

摘要翻译： 描述了用氮化物隧穿层编程和擦除非易失性存储器的方法。 非易失性存储器通过向栅极施加第一电压并使衬底接地以接通源极和漏极之间的沟道并且向漏极施加第二电压并且将源接地以感应通道中的电流来编程 从而在其中产生热电子。 热电子通过氮化物隧穿层注入到非挥发性的电荷捕获层中并被捕获在其中。 通过向漏极施加第一正偏压，向栅极施加第二正偏压，并且将源极和衬底接地以在沟道区域中产生热电子空穴来擦除非易失性存储器。 热电子空穴通过氮化物隧穿层注入电荷捕获层。

公开(公告)号：US06713821B2

公开(公告)日：2004-03-30

申请号：US10155619

申请日：2002-05-24

申请人： Tso-Hung Fan ,  Mu-Yi Liu ,  Kwang-Yang Chan ,  Yen-Hung Yeh ,  Tao-Cheng Lu

发明人： Tso-Hung Fan ,  Mu-Yi Liu ,  Kwang-Yang Chan ,  Yen-Hung Yeh ,  Tao-Cheng Lu

IPC分类号： H01L31062

CPC分类号： H01L27/1126 ,  H01L27/112

摘要： A mask ROM device is described. The mask ROM device includes a substrate, a gate, a double diffused source/drain region that comprises a first doped region and a second doped region, a channel region, a coding region, a dielectric layer and a word line. The gate is disposed on the substrate. The double diffused source/drain region is positioned beside the sides of the gate in the substrate, wherein the second doped region is located at the periphery of the first doped region in the substrate. The channel region is located between the double diffused source/drain region in the substrate. The coding region is disposed in the substrate at the intersection between the sides of the channel region and the double diffused source/drain region. The dielectric layer is disposed above the double diffused source/drain region, while the word line is disposed above the dielectric layer and the gate.

摘要翻译： 描述掩模ROM设备。 掩模ROM器件包括衬底，栅极，包括第一掺杂区域和第二掺杂区域的双扩散源极/漏极区域，沟道区域，编码区域，电介质层和字线。 栅极设置在基板上。 双扩散源极/漏极区域位于衬底中的栅极的侧面旁边，其中第二掺杂区域位于衬底中的第一掺杂区域的外围。 沟道区位于衬底中的双扩散源极/漏极区之间。 编码区域设置在沟道区域和双扩散源极/漏极区域的相交处的衬底中。 电介质层设置在双扩散源极/漏极区域的上方，而字线设置在电介质层和栅极之上。

公开(公告)号：US06643176B1

公开(公告)日：2003-11-04

申请号：US10064917

申请日：2002-08-29

申请人： Tso-Hung Fan ,  Chih-Chieh Yeh ,  Tao-Cheng Lu

发明人： Tso-Hung Fan ,  Chih-Chieh Yeh ,  Tao-Cheng Lu

IPC分类号： G11C1606

CPC分类号： G11C16/30 ,  G11C8/08 ,  G11C11/5642 ,  G11C2211/5634

摘要： A reference current generation circuit for the multiple bit flash memory provided by the present invention applies the same boosted word-line voltage to a voltage dividing circuit of the different reference current generation unit, so as to generate a gate voltage for the different reference current generation unit's reference cell to obtain the reference currents with different levels that are needed. Therefore, it effectively solves the problem of the reference currents having different drifts along with the variance of the temperature and the power voltage Vcc.

摘要翻译： 由本发明提供的用于多位闪存的参考电流产生电路将相同的升压字线电压施加到不同参考电流产生单元的分压电路，以产生用于不同参考电流产生的栅极电压 单位的参考单元，以获得所需水平不同的参考电流。 因此，它有效地解决了具有不同漂移的参考电流以及温度变化和电源电压Vcc的问题。

公开(公告)号：US06590266B1

公开(公告)日：2003-07-08

申请号：US10064906

申请日：2002-08-28

申请人： Mu-Yi Liu ,  Tso-Hung Fan ,  Kwang-Yang Chan ,  Yen-Hung Yeh ,  Tao-Cheng Lu

发明人： Mu-Yi Liu ,  Tso-Hung Fan ,  Kwang-Yang Chan ,  Yen-Hung Yeh ,  Tao-Cheng Lu

IPC分类号： H01L2994

CPC分类号： H01L27/11266 ,  H01L27/112

摘要： A 2-bit mask ROM device and a fabrication method thereof are described. The 2-bit mask ROM device includes a substrate; a gate structure, disposed on a part of the substrate; a 2-bit code region, configured in the substrate beside both sides of the gate structure; at least one spacer, disposed on both sides of the gate structure; a buried drain region, configured in the substrate beside both sides of the spacer; a doped region, configured in the substrate between the buried drain region and the 2-bit code region, wherein the dopant type of the doped region is different from that for the 2-bit code region and the dopant concentration in the doped region is higher than that in the 2-bit code region; an insulation layer, disposed above the buried drain region; and a word line disposed on the gate structures along a same row.

摘要翻译： 描述2位掩模ROM器件及其制造方法。 2位掩模ROM器件包括衬底; 栅极结构，设置在所述衬底的一部分上; 2位代码区，配置在栅极结构的两侧旁边的基板中; 设置在所述栅极结构的两侧的至少一个间隔物; 掩埋漏极区域，被构造在所述衬底旁边的所述间隔物的两侧; 掺杂区域，配置在掩埋漏极区域和2位码区域之间的衬底中，其中掺杂区域的掺杂剂类型与2位码区域的掺杂区域不同，并且掺杂区域中的掺杂剂浓度更高 比在2位代码区域; 绝缘层，设置在所述掩埋漏极区域的上方; 以及沿同一行设置在栅极结构上的字线。