公开(公告)号：US20080224252A1

公开(公告)日：2008-09-18

申请号：US12068635

申请日：2008-02-08

申请人： Kyoichi Suguro ,  Kiyotaka Miyano ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Takayuki Hiraoka ,  Yasushi Akasaka ,  Tsunetoshi Arikado

发明人： Kyoichi Suguro ,  Kiyotaka Miyano ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Takayuki Hiraoka ,  Yasushi Akasaka ,  Tsunetoshi Arikado

IPC分类号： H01L29/00

CPC分类号： H01L21/28194 ,  H01L21/28088 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/76262 ,  H01L21/823481 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66537 ,  H01L29/66545

摘要： In using an epitaxial growth method to selectively grow on a silicon substrate an epitaxial layer on which an element is to be formed, the epitaxial layer is formed so as to extend upward above a thermal oxide film that is an element isolating insulating film, in order to prevent formation of facets. Subsequently, unwanted portions of the epitaxial layer are removed by means of CMP to complete an STI element isolating structure.

摘要翻译： 在使用外延生长方法选择性地在硅衬底上生长其上要形成元素的外延层时，形成外延层，以便在作为元件隔离绝缘膜的热氧化膜上方向上延伸， 以防止形成小平面。 随后，通过CMP去除外延层的不需要的部分以完成STI元件隔离结构。

公开(公告)号：US06989316B2

公开(公告)日：2006-01-24

申请号：US10406281

申请日：2003-04-04

申请人： Kyoichi Suguro ,  Kiyotaka Miyano ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Takayuki Hiraoka ,  Yasushi Akasaka ,  Tsunetoshi Arikado

发明人： Kyoichi Suguro ,  Kiyotaka Miyano ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Takayuki Hiraoka ,  Yasushi Akasaka ,  Tsunetoshi Arikado

IPC分类号： H01L21/20

CPC分类号： H01L21/28194 ,  H01L21/28088 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/76262 ,  H01L21/823481 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66537 ,  H01L29/66545

摘要： In using an epitaxial growth method to selectively grow on a silicon substrate an epitaxial layer on which an element is to be formed, the epitaxial layer is formed so as to extend upward above a thermal oxide film that is an element isolating insulating film, in order to prevent formation of facets. Subsequently, unwanted portions of the epitaxial layer are removed by means of CMP to complete an STI element isolating structure.

公开(公告)号：US06617226B1

公开(公告)日：2003-09-09

申请号：US09609107

申请日：2000-06-30

申请人： Kyoioni Suguro ,  Kiyotaka Miyano ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Takayuki Hiraoka ,  Yasushi Akasaka ,  Tsunetoshi Arikado

发明人： Kyoioni Suguro ,  Kiyotaka Miyano ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Takayuki Hiraoka ,  Yasushi Akasaka ,  Tsunetoshi Arikado

IPC分类号： H01L2120

CPC分类号： H01L21/28194 ,  H01L21/28088 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/76262 ,  H01L21/823481 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66537 ,  H01L29/66545

摘要： In using an epitaxial growth method to selectively grow on a silicon substrate an epitaxial layer on which an element is to be formed, the epitaxial layer is formed so as to extend upward above a thermal oxide film that is an element isolating insulating film, in order to prevent formation of facets. Subsequently, unwanted portions of the epitaxial layer are removed by means of CMP to complete an STI element isolating structure.

摘要翻译： 在使用外延生长方法选择性地在硅衬底上生长其上要形成元素的外延层时，形成外延层，以便在作为元件隔离绝缘膜的热氧化膜上方向上延伸， 以防止形成小平面。 随后，通过CMP去除外延层的不需要的部分以完成STI元件隔离结构。

公开(公告)号：US07772671B2

公开(公告)日：2010-08-10

申请号：US12068635

申请日：2008-02-08

申请人： Kyoichi Suguro ,  Kiyotaka Miyano ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Takayuki Hiraoka ,  Yasushi Akasaka ,  Tsunetoshi Arikado

发明人： Kyoichi Suguro ,  Kiyotaka Miyano ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Takayuki Hiraoka ,  Yasushi Akasaka ,  Tsunetoshi Arikado

IPC分类号： H01L29/00

CPC分类号： H01L21/28194 ,  H01L21/28088 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/76262 ,  H01L21/823481 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66537 ,  H01L29/66545

摘要： A semiconductor device including a semiconductor substrate having on its surface a recess and at least one projection formed in the recess. The projection has a channel region and an element isolating insulating film is formed in the recess. A MIS type semiconductor element is formed on the semiconductor substrate and includes a gate electrode formed on the channel region of the projection via a gate insulating film. Source and drain regions are formed to pinch the channel region of the projection therebetween. A channel region of the MIS type semiconductor element is formed to reach the at least one projection located adjacent to the MIS type semiconductor element in its channel width direction via the recess. A top surface of the at least one projection is located higher than the top surface of the element isolating insulating film by 20 nm or more.

摘要翻译： 一种半导体器件，包括在其表面上具有凹部的半导体衬底和形成在凹部中的至少一个突起。 突起具有沟道区域，并且在凹部中形成元件隔离绝缘膜。 MIS半导体元件形成在半导体衬底上，并且包括通过栅极绝缘膜形成在突起的沟道区上的栅电极。 形成源区和漏区以夹住其间的突起的沟道区。 MIS型半导体元件的沟道区域形成为经由凹部在其沟道宽度方向上到达位于与MIS型半导体元件相邻的至少一个突起。 所述至少一个突起的顶表面比所述元件隔离绝缘膜的顶表面高20nm或更大。

公开(公告)号：US20080211004A1

公开(公告)日：2008-09-04

申请号：US12040224

申请日：2008-02-29

申请人： Yoshio OZAWA ,  Ichiro Mizushima ,  Takashi Suzuki ,  Hirokazu Ishida ,  Yoshitaka Tsunashima

发明人： Yoshio OZAWA ,  Ichiro Mizushima ,  Takashi Suzuki ,  Hirokazu Ishida ,  Yoshitaka Tsunashima

IPC分类号： H01L29/32 ,  H01L21/20

CPC分类号： H01L29/788 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/04

摘要： A semiconductor device includes a silicon crystal layer on an insulating layer, the silicon crystal layer containing a crystal lattice mismatch plane, a memory cell array portion on the silicon crystal layer, the memory cell array portion including memory strings, each of the memory strings including nonvolatile memory cell transistors connected in series in a first direction, the memory strings being arranged in a second direction orthogonal to the first direction, the crystal lattice mismatch plane crossing the silicon crystal along the second direction without passing under gates of the nonvolatile memory cell transistors as viewed from a top of the silicon crystal layer, or crossing the silicon crystal along the first direction with passing under gates of the nonvolatile memory cell transistors as viewed from the top of the silicon crystal layer.

摘要翻译： 半导体器件包括绝缘层上的硅晶体层，含有晶格失配平面的硅晶体层，硅晶体层上的存储单元阵列部分，存储单元阵列部分包括存储器串，每个存储器串包括 所述非易失性存储单元晶体管沿第一方向串联连接，所述存储器串沿与所述第一方向正交的第二方向布置，所述晶格失配面沿着所述第二方向与所述硅晶体交叉，而不通过所述非易失性存储单元晶体管的栅极 从硅晶体层的顶部观察，或者从硅晶体层的顶部观察时沿着非易失性存储单元晶体管的栅极通过硅晶体沿第一方向。

公开(公告)号：US06794713B2

公开(公告)日：2004-09-21

申请号：US10655022

申请日：2003-09-05

申请人： Ichiro Mizushima ,  Shigehiko Saida ,  Takeo Furuhata ,  Yoshitaka Tsunashima

发明人： Ichiro Mizushima ,  Shigehiko Saida ,  Takeo Furuhata ,  Yoshitaka Tsunashima

IPC分类号： H01L2976

CPC分类号： H01L29/66477 ,  H01L21/28052 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/456 ,  H01L29/665

摘要： SiGe or SiC films are selectively grown on source/drain regions, followed by selectively growing silicon. A monocrystalline film having a high dislocation density or a polycrystalline film can be grown in growing the silicon film by making the C or Ge concentration higher than a predetermined level. The silicon layer on each of the source/drain regions is not monocrystalline or, even if monocrystalline, has a high density of dislocation. Therefore, the silicon film formed thereon is in the form of a monocrystalline silicon film having a high dislocation density or a polycrystalline silicon film. It is possible to suppress an impurity diffusion to reach a deep region caused by channeling of ions generated in the doping step by means of an ion implantation.

摘要翻译： SiGe或SiC膜选择性地在源极/漏极区域上生长，随后选择性地生长硅。 通过使C或Ge浓度高于预定水平，可以在生长硅膜时生长具有高位错密度的单晶膜或多晶膜。 源极/漏极区域中的每一个上的硅层不是单晶的，即使单晶也具有高密度的位错。 因此，其上形成的硅膜是具有高位错密度的单晶硅膜或多晶硅膜的形式。 可以通过离子注入来抑制在掺杂步骤中产生的离子的沟道引起的深度区域的杂质扩散。

公开(公告)号：US06335251B1

公开(公告)日：2002-01-01

申请号：US09824215

申请日：2001-04-03

申请人： Kiyotaka Miyano ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Tomohiro Saito

发明人： Kiyotaka Miyano ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Tomohiro Saito

IPC分类号： H01L21336

摘要： A semiconductor apparatus on which a MOS transistor having an elevated source and drain structure is formed is arranged to have a gate electrode which is formed on the surface of a silicon substrate through an insulating film. An elevated source film and an elevated drain film each having at least a surface portion constituted by a metal silicide film, being conductive and elevated over the surface of the silicon substrate are formed on a source region and a drain region on the surface of the silicon substrate. Thus, a MOS transistor having a structure in which the surfaces of the source region and the drain region are elevated over the surface of the silicon substrate is formed. A first gate-side-wall insulating film is formed on the side wall of the gate electrode of the MOS transistor and having a bottom surface formed apart from the surface of the silicon substrate. A second gate-side-wall insulating film is formed between the first gate-side-wall insulating film and the gate electrode and on the bottom surface of the first gate-side-wall insulating film. The portion formed on the bottom surface exists in an inner bottom surface portion of the bottom surface of the first gate-sidewall insulating film adjacent to the gate electrode. The elevated source film and the elevated drain film are free from any facet in portions made contact with the first gate-side-wall insulating film.

公开(公告)号：US07879658B2

公开(公告)日：2011-02-01

申请号：US12040224

申请日：2008-02-29

申请人： Yoshio Ozawa ,  Ichiro Mizushima ,  Takashi Suzuki ,  Hirokazu Ishida ,  Yoshitaka Tsunashima

发明人： Yoshio Ozawa ,  Ichiro Mizushima ,  Takashi Suzuki ,  Hirokazu Ishida ,  Yoshitaka Tsunashima

IPC分类号： H01L21/00 ,  H01L29/04

CPC分类号： H01L29/788 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/04

摘要： A semiconductor device includes a silicon crystal layer on an insulating layer, the silicon crystal layer containing a crystal lattice mismatch plane, a memory cell array portion on the silicon crystal layer, the memory cell array portion including memory strings, each of the memory strings including nonvolatile memory cell transistors connected in series in a first direction, the memory strings being arranged in a second direction orthogonal to the first direction, the crystal lattice mismatch plane crossing the silicon crystal along the second direction without passing under gates of the nonvolatile memory cell transistors as viewed from a top of the silicon crystal layer, or crossing the silicon crystal along the first direction with passing under gates of the nonvolatile memory cell transistors as viewed from the top of the silicon crystal layer.

摘要翻译： 半导体器件包括绝缘层上的硅晶体层，含有晶格失配平面的硅晶体层，硅晶体层上的存储单元阵列部分，存储单元阵列部分包括存储器串，每个存储器串包括 所述非易失性存储单元晶体管沿第一方向串联连接，所述存储器串沿与所述第一方向正交的第二方向布置，所述晶格失配面沿着所述第二方向与所述硅晶体交叉，而不通过所述非易失性存储单元晶体管的栅极 从硅晶体层的顶部观察，或者从硅晶体层的顶部观察时沿着非易失性存储单元晶体管的栅极通过硅晶体沿第一方向。

公开(公告)号：US20090121279A1

公开(公告)日：2009-05-14

申请号：US12249354

申请日：2008-10-10

申请人： Hirokazu Ishida ,  Takashi Suzuki ,  Yoshio Ozawa ,  Ichiro Mizushima ,  Yoshitaka Tsunashima

发明人： Hirokazu Ishida ,  Takashi Suzuki ,  Yoshio Ozawa ,  Ichiro Mizushima ,  Yoshitaka Tsunashima

IPC分类号： H01L21/20 ,  H01L29/786

CPC分类号： H01L27/11521 ,  H01L21/84 ,  H01L27/11524 ,  H01L27/1203

摘要： A semiconductor device includes a single crystal silicon substrate an insulating layer partially formed on the single crystal silicon substrate, a single crystal silicon layer formed on the single crystal silicon substrate and the insulating layer, and containing a defect layer resulting from an excessive group IV element, and a plurality of first gate structures for memory cells, each including a first gate insulating film formed on the single crystal silicon layer, a charge storage layer formed on the first gate insulating film, a second gate insulating film formed on the charge storage layer, and a control gate electrode formed on the second gate insulating film.

摘要翻译： 半导体器件包括单晶硅衬底，部分地形成在单晶硅衬底上的绝缘层，形成在单晶硅衬底上的单晶硅层和绝缘层，并且包含由过量IV族元素产生的缺陷层 以及多个用于存储单元的第一栅极结构，每个包括形成在单晶硅层上的第一栅极绝缘膜，形成在第一栅极绝缘膜上的电荷存储层，形成在电荷存储层上的第二栅极绝缘膜 以及形成在第二栅极绝缘膜上的控制栅电极。

公开(公告)号：US06713359B1

公开(公告)日：2004-03-30

申请号：US09564191

申请日：2000-05-04

申请人： Ichiro Mizushima ,  Shigehiko Saida ,  Takeo Furuhata ,  Yoshitaka Tsunashima

发明人： Ichiro Mizushima ,  Shigehiko Saida ,  Takeo Furuhata ,  Yoshitaka Tsunashima

IPC分类号： H01L21336

CPC分类号： H01L29/66477 ,  H01L21/28052 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/456 ,  H01L29/665

摘要： SiGe or SiC films are selectively grown on source/drain regions, followed by selectively growing silicon. A monocrystalline film having a high dislocation density or a polycrystalline film can be grown in growing the silicon film by making the C or Ge concentration higher than a predetermined level. The silicon layer on each of the source/drain regions is not monocrystalline or, even if monocrystalline, has a high density of dislocation. Therefore, the silicon film formed thereon is in the form of a monocrystalline silicon film having a high dislocation density or a polycrystalline silicon film. It is possible to suppress an impurity diffusion to reach a deep region caused by channeling of ions generated in the doping step by means of an ion implantation.

摘要翻译： SiGe或SiC膜选择性地在源极/漏极区域上生长，随后选择性地生长硅。 通过使C或Ge浓度高于预定水平，可以在生长硅膜时生长具有高位错密度的单晶膜或多晶膜。 源极/漏极区域中的每一个上的硅层不是单晶的，即使单晶也具有高密度的位错。 因此，其上形成的硅膜是具有高位错密度的单晶硅膜或多晶硅膜的形式。 可以通过离子注入来抑制在掺杂步骤中产生的离子的沟道引起的深度区域的杂质扩散。