中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

22 records (took 0.014 seconds)

    MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
    11.
    发明申请
    MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20200185597A1

    公开(公告)日：2020-06-11

    申请号：US16216969

    申请日：2018-12-11

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Kun-Ju Li ,  Hsin-Jung Liu ,  I-Ming Tseng ,  Chau-Chung Hou ,  Yu-Lung Shih ,  Fu-Chun Hsiao ,  Hui-Lin Wang ,  Tzu-Hsiang Hung ,  Chih-Yueh Li ,  Ang Chan ,  Jing-Yin Jhang

    IPC: H01L43/02 ,  H01L27/22 ,  H01L43/10 ,  H01L43/12

    Abstract: A memory device includes an insulation layer, a memory cell region and an alignment mark region are defined on the insulation layer, an interconnection structure disposed in the insulation layer, a dielectric layer disposed on the insulation layer and the interconnection structure, the dielectric layer is disposed within the memory cell region and the alignment mark region, a conductive via plug disposed on the interconnection structure within the memory cell region, the conductive via plug has a concave top surface, an alignment mark trench penetrating the dielectric layer within the alignment mark region, a bottom electrode disposed on the conductive via plug within the memory cell region and disposed in the alignment mark trench within the alignment mark region, and a magnetic tunnel junction (MTJ) structure disposed on the bottom electrode within the memory cell region and disposed in the alignment mark trench within the alignment mark region.

    METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE
    12.
    发明申请
    METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE 有权

    公开(公告)号：US20250169079A1

    公开(公告)日：2025-05-22

    申请号：US18404839

    申请日：2024-01-04

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Fu-Shou Tsai ,  Chau-Chung Hou ,  Yong-Yi Lin ,  Yang-Ju Lu ,  Yu-Lung Shih ,  Ren-Peng Huang ,  Ching-Yang Chuang

    IPC: H10B61/00

    Abstract: A method of forming a semiconductor structure. A memory structure is formed on a substrate in the memory array region. A dielectric layer is deposited over the memory array region and peripheral region to cover the memory structure. A reverse etching process is performed to remove part of the dielectric layer from the central area of the memory array region, thereby forming an upwardly protruding wall structure along perimeter of the memory array region. The remaining thickness of the dielectric layer in the central area is equal to the sum of a polishing buffer thickness and a target thickness. A first polishing process is performed to remove the upwardly protruding wall structure from the memory array region. A second polishing process is performed to remove upper portion of the dielectric layer with the polishing buffer thickness from the memory array region.

    ALIGNMENT MARK STRUCTURE AND METHOD OF FABRICATING THE SAME
    15.
    发明申请
    ALIGNMENT MARK STRUCTURE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20210249357A1

    公开(公告)日：2021-08-12

    申请号：US16786919

    申请日：2020-02-10

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Kun-Ju Li ,  Jhih-Yuan Chen ,  Hsin-Jung Liu ,  Chau-Chung Hou ,  Yu-Lung Shih ,  Ang Chan ,  Fu-Chun Hsiao ,  Ji-Min Lin ,  Chun-Han Chen

    IPC: H01L23/544 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12

    Abstract: An alignment mark structure includes a dielectric layer. A trench is embedded in the dielectric layer. An alignment mark fills up the trench, wherein the alignment mark includes a metal layer covering the trench. A first material layer covers and contacts the metal layer. A second material layer covers and contacts the first material layer. A third material layer covers and contacts the second material layer. The first material layer, the second material layer, and the third material layer are independently comprises silicon nitride, silicon oxide, tantalum-containing material, aluminum-containing material, titanium-containing material, or a low-k dielectric having a dielectric constant smaller than 2.7, and a reflectance of the first material layer is larger than a reflectance of the second material layer, the reflectance of the second material layer is larger than a reflectance of the third material layer.

    Manufacturing method of memory device
    16.
    发明授权
    Manufacturing method of memory device 有权

    公开(公告)号：US10804461B1

    公开(公告)日：2020-10-13

    申请号：US16517693

    申请日：2019-07-22

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hsin-Jung Liu ,  Kun-Ju Li ,  Ang Chan ,  Chau-Chung Hou ,  Yu-Lung Shih

    IPC: H01L21/00 ,  H01L43/12 ,  H01L43/02

    Abstract: A method for manufacturing a memory device is provided, the method includes the following steps: firstly, providing a dielectric layer, then simultaneously forming a contact window and an alignment mark trench in the dielectric layer, wherein the contact window exposes a lower metal line, then forming a conductive layer on the surface of the dielectric layer, in the contact window and in the alignment mark trench, performing a planarization step on the conductive layer, and leaving a residue in the alignment mark trench. Subsequently, a nitrogen plasma step (N2 plasma) is performed on the dielectric layer, a cleaning step is performed to remove the residue in the alignment mark trench, and a patterned magnetic tunneling junction, MTJ) film is laminated on the contact window.

Patent Agency Ranking