公开(公告)号：US20190221517A1

公开(公告)日：2019-07-18

申请号：US15893676

申请日：2018-02-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Chia-Huei Lin ,  Kuo-Yuh Yang

IPC: H01L23/528 ,  H01L29/08 ,  H01L27/12 ,  H01L29/78

Abstract: A semiconductor device on silicon-on-insulator (SOI) substrate includes: a first gate line and a second gate line extending along a first direction, a third gate extending along a second direction and between the first gate line and the second gate line, and a drain region adjacent to one side of the third gate line. Preferably, the third gate line includes a first protrusion overlapping the drain region.

公开(公告)号：US20170036905A1

公开(公告)日：2017-02-09

申请号：US15295997

申请日：2016-10-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Che Chen ,  Te-Yuan Wu ,  Chia-Huei Lin ,  Hui-Min Wu ,  Kun-Che Hsieh ,  Kuan-Yu Wang ,  Chung-Yi Chiu

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B81B3/0075 ,  B81B2207/07 ,  B81C1/00246 ,  B81C1/00801 ,  B81C2201/014 ,  B81C2203/0714 ,  B81C2203/0735

Abstract: A MEMS structure includes a substrate, an inter-dielectric layer on a front side of the substrate, a MEMS component on the inter-dielectric layer, and a chamber disposed within the inter-dielectric layer and through the substrate. The chamber has an opening at a backside of the substrate. An etch stop layer is disposed within the inter-dielectric layer. The chamber has a ceiling opposite to the opening and a sidewall joining the ceiling. The sidewall includes a portion of the etch stop layer.

Abstract translation: MEMS结构包括衬底，在衬底的前侧上的介电层，介电层之间的MEMS组件，以及设置在介质间介质层内并通过衬底的室。 该腔室在衬底的背面具有开口。 蚀刻停止层设置在介电层内。 该室具有与开口相对的天花板和连接天花板的侧壁。 侧壁包括蚀刻停止层的一部分。

公开(公告)号：US20240379492A1

公开(公告)日：2024-11-14

申请号：US18780438

申请日：2024-07-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang ,  Chia-Huei Lin

IPC: H01L23/367 ,  H01L21/768 ,  H01L23/00 ,  H01L23/373 ,  H01L23/48 ,  H01L23/485 ,  H01L25/00 ,  H01L25/07

Abstract: A semiconductor structure with a heat dissipation structure includes a first device wafer includes a front side and a back side. A first transistor is disposed on the front side. The first transistor includes a first gate structure disposed on the front side. Two first source/drain doping regions are embedded within the first device wafer at two side of the first gate structure. A channel region is disposed between the two first source/drain doping regions and embedded within the first device wafer. A first dummy metal structure contacts the back side of the first device wafer, and overlaps the channel region.

公开(公告)号：US20240203785A1

公开(公告)日：2024-06-20

申请号：US18179377

申请日：2023-03-07

Applicant: United Microelectronics Corp.

Inventor： Ching-Pin Hsu ,  Shih Hung Yang ,  Chu Chun Chang ,  Kuo-Yuh Yang ,  Chia-Huei Lin

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L29/06

CPC classification number: H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5283 ,  H01L29/0649

Abstract: A semiconductor device includes a conductive structure, a first dielectric layer, a second dielectric layer and a liner layer. The conductive structure is located on a substrate. The first dielectric layer covers the conductive structure and the substrate. The second dielectric layer is located on the first dielectric layer. An air gap is present in the first dielectric layer and the second dielectric layer, and is located above the conductive structure. The liner layer covers and surrounds a middle portion of the air gap.

公开(公告)号：US11721757B2

公开(公告)日：2023-08-08

申请号：US17391048

申请日：2021-08-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Chia-Huei Lin ,  Kuo-Yuh Yang

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L21/266 ,  H01L21/285 ,  H01L29/78

CPC classification number: H01L29/7824 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/4238 ,  H01L29/66681 ,  H01L29/78624 ,  H01L21/266 ,  H01L21/28518 ,  H01L29/665

Abstract: A LDMOS device includes a semiconductor layer on an insulation layer and a ring shape gate on the semiconductor layer. The ring shape gate includes a first gate portion, a second gate portion, and two third gate portions connecting the first gate portion and the second gate portion. The semiconductor device further includes a first drain region and a second drain region formed in the semiconductor layer at two sides of the ring shape gate, a plurality of source regions formed in the semiconductor layer surrounded by the ring shape gate, a plurality of body contact regions formed in the semiconductor layer and arranged between the source regions, and a first body implant region and a second body implant region formed in the semiconductor layer, respectively underlying part of the first gate portion and part of the second gate portion, and being connected by the body contact regions.

公开(公告)号：US11658087B2

公开(公告)日：2023-05-23

申请号：US17080858

申请日：2020-10-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang ,  Chia-Huei Lin

IPC: H01L23/367 ,  H01L21/48

CPC classification number: H01L23/367 ,  H01L21/4803

Abstract: A high resistivity wafer with a heat dissipation structure includes a high resistivity wafer and a metal structure. The high resistivity wafer includes a heat dissipation region and a device support region. The high resistivity wafer consists of an insulating material. The metal structure is only embedded within the heat dissipation region of the high resistivity wafer. The metal structure surrounds the device support region.

公开(公告)号：US11476192B2

公开(公告)日：2022-10-18

申请号：US16734373

申请日：2020-01-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Chia-Huei Lin ,  Kuo-Yuh Yang

IPC: H01L23/528 ,  H01L29/08 ,  H01L29/78 ,  H01L27/12 ,  H01L29/423 ,  H01L29/45 ,  H01L21/768 ,  H03F3/16 ,  H01L21/321 ,  H01L21/84

Abstract: A semiconductor device includes: a first gate line and a second gate line extending only along a first direction, a third gate line and a fourth gate line extending along the first direction and between the first gate line and the second gate line, a fifth gate line and a sixth gate line extending along a second direction between the first gate line and the second gate line and intersecting the third gate line and the fourth gate line, and first contact plugs on the first gate line. Preferably, the first direction is perpendicular to the second direction and the first gate line and the second gate line are directly connected to the fifth gate line and the sixth gate line.

公开(公告)号：US11462489B2

公开(公告)日：2022-10-04

申请号：US17401335

申请日：2021-08-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang ,  Chia-Huei Lin ,  Chu-Chun Chang

IPC: H01L23/00 ,  H01L27/12 ,  H01L21/84 ,  H01L23/58 ,  H01L23/66 ,  H01L27/06

Abstract: A method of forming integrated circuit device, including: providing a substrate; forming an integrated circuit region on the substrate, the integrated circuit region comprising a dielectric stack; forming a seal ring in the dielectric stack and around a periphery of the integrated circuit region; forming a trench around the seal ring and the trench exposing a sidewall of the dielectric stack; forming a moisture blocking layer continuously covering the integrated circuit region and extending to the sidewall of the dielectric stack, thereby sealing a boundary between two adjacent dielectric films in the dielectric stack; and forming a passivation layer over the moisture blocking layer.

公开(公告)号：US20220085184A1

公开(公告)日：2022-03-17

申请号：US17068840

申请日：2020-10-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Heng-Ching Lin ,  Yu-Teng Tseng ,  Chu-Chun Chang ,  Kuo-Yuh Yang ,  Chia-Huei Lin

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/78

Abstract: A semiconductor device includes a gate structure on a substrate, in which the gate structure includes a main branch extending along a first direction on the substrate and a sub-branch extending along a second direction adjacent to the main branch. The semiconductor device also includes a first doped region overlapping the main branch and the sub-branch according to a top view and a second doped region overlapping the first doped region.

公开(公告)号：US20210359131A1

公开(公告)日：2021-11-18

申请号：US17391048

申请日：2021-08-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Chia-Huei Lin ,  Kuo-Yuh Yang

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A LDMOS device includes a semiconductor layer on an insulation layer and a ring shape gate on the semiconductor layer. The ring shape gate includes a first gate portion, a second gate portion, and two third gate portions connecting the first gate portion and the second gate portion. The semiconductor device further includes a first drain region and a second drain region formed in the semiconductor layer at two sides of the ring shape gate, a plurality of source regions formed in the semiconductor layer surrounded by the ring shape gate, a plurality of body contact regions formed in the semiconductor layer and arranged between the source regions, and a first body implant region and a second body implant region formed in the semiconductor layer, respectively underlying part of the first gate portion and part of the second gate portion, and being connected by the body contact regions.