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公开(公告)号：US20200013949A1
公开(公告)日：2020-01-09
申请号：US16056551
申请日：2018-08-07
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ya-Sheng Feng , Hung-Chan Lin , Yu-Ping Wang , Yu-Chun Chen , Chiu-Jung Chiu
Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a magnetic tunneling junction (MTJ) on the first IMD layer; forming a liner on the MTJ and the first IMD layer; removing part of the liner to form a spacer adjacent to the MTJ; and forming a second IMD layer on the first IMD layer.
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公开(公告)号：US20240357943A1
公开(公告)日：2024-10-24
申请号：US18760005
申请日：2024-06-30
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chiu-Jung Chiu , Ya-Sheng Feng , I-Ming Tseng , Yi-An Shih , Yu-Chun Chen , Yi-Hui Lee , Chung-Liang Chu , Hsiu-Hao Hu
Abstract: A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.
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公开(公告)号：US20220029087A1
公开(公告)日：2022-01-27
申请号：US16997922
申请日：2020-08-19
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Yu-Chun Chen , Yen-Chun Liu , Ya-Sheng Feng , Chiu-Jung Chiu , I-Ming Tseng , Yi-An Shih , Yi-Hui Lee , Chung-Liang Chu , Hsiu-Hao Hu
Abstract: A semiconductor device includes a substrate having a magnetic random access memory (MRAM) region and a logic region, a first metal interconnection on the MRAM region, a second metal interconnection on the logic region, a stop layer extending from the first metal interconnection to the second metal interconnection, and a magnetic tunneling junction (MTJ) on the first metal interconnection. Preferably, the stop layer on the first metal interconnection and the stop layer on the second metal interconnection have different thicknesses.
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公开(公告)号：US20200243753A1
公开(公告)日：2020-07-30
申请号：US16850003
申请日：2020-04-16
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Yu-Chun Chen , Ya-Sheng Feng , Chiu-Jung Chiu , Hung-Chan Lin
Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the MTJ, and a second spacer on another side of the MTJ, in which the first spacer and the second spacer are asymmetric. Specifically, the MTJ further includes a first bottom electrode disposed on a metal interconnection, a capping layer on the bottom electrode, and a top electrode on the capping layer, in which a top surface of the first spacer is even with a top surface of the top electrode and a top surface of the second spacer is lower than the top surface of the top electrode and higher than the top surface of the capping layer.
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公开(公告)号：US20200075840A1
公开(公告)日：2020-03-05
申请号：US16148852
申请日：2018-10-01
Applicant: United Microelectronics Corp.
Inventor： Ya-Sheng Feng , Yu-Chun Chen , Chiu-Jung Chiu , Hung-Chan Lin
IPC: H01L43/02 , G11C11/16 , H01F10/32 , H01L23/528 , H01L23/522 , H01L23/532 , H01L43/12 , H01L27/22 , H01F41/34
Abstract: A magnetoresistive memory cell is provided including a substrate. An inter-layer dielectric layer is disposed on the substrate. A via structure is disposed in the inter-layer dielectric layer. A magnetic pinned layer is disposed on the via structure. A tunnel barrier layer is disposed on the magnetic pinned layer to cover a top and a sidewall of the magnetic pinned layer, wherein the tunnel barrier layer comprises a horizontal extending portion outward from a bottom of the sidewall. A magnetic free layer with a -like structure is disposed on the tunnel barrier layer, wherein the magnetic free layer is isolated from the magnetic pinned layer by the tunnel bather layer. A spacer is disposed on the sidewall of the magnetic free layer. The spacer extends to the inter-layer dielectric layer.
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Patent Agency Ranking
公开(公告)号：US20190035674A1
公开(公告)日：2019-01-31
申请号：US15681419
申请日：2017-08-20
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chiu-Jung Chiu , Hung-Chan Lin , Yu-Chun Chen
IPC: H01L21/762 , H01L21/02 , H01L21/768 , H01L29/94 , H01L27/06 , H01L49/02 , H01L21/8234 , H01L21/28
Abstract: An integrated circuit includes a first insulation layer, a bottom plate, a first patterned dielectric layer, a medium plate, a second patterned dielectric layer, and a top plate. The first patterned dielectric layer is disposed on the bottom plate. The medium plate is disposed on the first patterned dielectric layer. At least a part of the first patterned dielectric layer and the medium plate and a part of the bottom plate are disposed in a first trench penetrating the first insulation layer. The bottom plate, the first patterned dielectric layer, and the medium plate constitute a first metal-insulator-metal (MIM) capacitor. The second patterned dielectric layer is disposed on the medium plate. The top plate is disposed on the second patterned dielectric layer. The medium plate, the second patterned dielectric layer, and the top plate constitute a second MIM capacitor. The bottom plate is electrically connected with the top plate.
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公开(公告)号：US12063871B2
公开(公告)日：2024-08-13
申请号：US18230189
申请日：2023-08-04
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chiu-Jung Chiu , Ya-Sheng Feng , I-Ming Tseng , Yi-An Shih , Yu-Chun Chen , Yi-Hui Lee , Chung-Liang Chu , Hsiu-Hao Hu
Abstract: A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.
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公开(公告)号：US20230380296A1
公开(公告)日：2023-11-23
申请号：US18230189
申请日：2023-08-04
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chiu-Jung Chiu , Ya-Sheng Feng , I-Ming Tseng , Yi-An Shih , Yu-Chun Chen , Yi-Hui Lee , Chung-Liang Chu , Hsiu-Hao Hu
Abstract: A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.
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公开(公告)号：US11765983B2
公开(公告)日：2023-09-19
申请号：US17972542
申请日：2022-10-24
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chiu-Jung Chiu , Ya-Sheng Feng , I-Ming Tseng , Yi-An Shih , Yu-Chun Chen , Yi-Hui Lee , Chung-Liang Chu , Hsiu-Hao Hu
Abstract: A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.
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公开(公告)号：US20230040932A1
公开(公告)日：2023-02-09
申请号：US17972542
申请日：2022-10-24
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chiu-Jung Chiu , Ya-Sheng Feng , I-Ming Tseng , Yi-An Shih , Yu-Chun Chen , Yi-Hui Lee , Chung-Liang Chu , Hsiu-Hao Hu
Abstract: A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.
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