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公开(公告)号:US20200235227A1
公开(公告)日:2020-07-23
申请号:US16282323
申请日:2019-02-22
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Chung-Fu Chang , Kuan-Hung Chen , Guang-Yu Lo , Chun-Chia Chen , Chun-Tsen Lu
Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a gate dielectric layer on the fin-shaped structure; forming a gate electrode on the fin-shaped structure; performing a nitridation process to implant ions into the gate dielectric layer adjacent to two sides of the gate electrode; and forming an epitaxial layer adjacent to two sides of the gate electrode.
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公开(公告)号:US10403715B2
公开(公告)日:2019-09-03
申请号:US16222709
申请日:2018-12-17
Applicant: United Microelectronics Corp.
Inventor: Rung-Yuan Lee , Chun-Tsen Lu , Kuan-Hung Chen
IPC: H01L29/06 , H01L29/423 , H01L29/41 , H01L29/417 , H01L23/535 , H01L21/306 , H01L29/66 , H01L21/308 , H01L29/786 , H01L21/84 , H01L27/12
Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a semiconductor nanowire, a gate structure, a first metal nanowire and a second metal nanowire. The semiconductor nanowire is disposed vertically on the substrate. The gate structure surrounds a middle portion of the semiconductor nanowire. The first metal nanowire is located on a side of the semiconductor nanowire and is electronically connected to a lower portion of the semiconductor nanowire. The second metal nanowire is located on the other side of the semiconductor nanowire and is electronically connected to the gate structure.
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公开(公告)号:US10043807B1
公开(公告)日:2018-08-07
申请号:US15641236
申请日:2017-07-04
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Rung-Yuan Lee , Yu-Cheng Tung , Chun-Tsen Lu , En-Chiuan Liou , Kuan-Hung Chen
IPC: H01L21/00 , H01L27/00 , H01L29/00 , H01L27/092 , H01L27/02 , H01L29/08 , H01L29/78 , H01L21/8238 , H01L29/66 , H01L21/8234 , H01L21/02
Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a plural fin structures, two gates, a protection layer and an interlayer dielectric layer. The fin structures are disposed on a substrate. The two gates are disposed on the substrate across the fin structures. The protection layer is disposed on the substrate, surrounded sidewalls of the two gates. The interlayer dielectric layer is disposed on the substrate, covering the fin structures and the two gates.
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