公开(公告)号：US20190140051A1

公开(公告)日：2019-05-09

申请号：US16222709

申请日：2018-12-17

Applicant: United Microelectronics Corp.

Inventor： Rung-Yuan Lee ,  Chun-Tsen Lu ,  Kuan-Hung Chen

IPC: H01L29/06 ,  H01L29/66 ,  H01L27/12 ,  H01L21/84 ,  H01L29/417 ,  H01L29/786 ,  H01L21/308 ,  H01L29/423 ,  H01L21/306 ,  H01L23/535 ,  H01L29/41

CPC classification number: H01L29/0676 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/84 ,  H01L23/535 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/413 ,  H01L29/41733 ,  H01L29/41741 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/78642

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a semiconductor nanowire, a gate structure, a first metal nanowire and a second metal nanowire. The semiconductor nanowire is disposed vertically on the substrate. The gate structure surrounds a middle portion of the semiconductor nanowire. The first metal nanowire is located on a side of the semiconductor nanowire and is electronically connected to a lower portion of the semiconductor nanowire. The second metal nanowire is located on the other side of the semiconductor nanowire and is electronically connected to the gate structure.

公开(公告)号：US10204986B1

公开(公告)日：2019-02-12

申请号：US15783823

申请日：2017-10-13

Applicant: United Microelectronics Corp.

Inventor： Rung-Yuan Lee ,  Chun-Tsen Lu ,  Kuan-Hung Chen

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/41 ,  H01L29/417 ,  H01L23/535 ,  H01L21/306 ,  H01L29/66 ,  H01L21/308 ,  H01L29/786 ,  H01L21/84 ,  H01L27/12

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a semiconductor nanowire, a gate structure, a first metal nanowire and a second metal nanowire. The semiconductor nanowire is disposed vertically on the substrate. The gate structure surrounds a middle portion of the semiconductor nanowire. The first metal nanowire is located on a side of the semiconductor nanowire and is electronically connected to a lower portion of the semiconductor nanowire. The second metal nanowire is located on the other side of the semiconductor nanowire and is electronically connected to the gate structure.

公开(公告)号：US10153353B1

公开(公告)日：2018-12-11

申请号：US15613278

申请日：2017-06-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Rung-Yuan Lee ,  Chih-Wei Yang

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/40 ,  H01L29/66 ,  H01L29/10

Abstract: The present invention provides a method for forming a semiconductor structure, including the following steps: first, a substrate is provided, an interlayer dielectric (ILD) is formed on the substrate, a first dummy gate is formed in the ILD, wherein the first dummy gate includes a dummy gate electrode and two spacers disposed on two sides of the dummy gate electrode respectively. Next, two contact holes are formed in the ILD at two sides of the first dummy gate respectively. Afterwards, the dummy gate electrode is removed, so as to form a gate recess in the ILD, a first material layer is filled in the gate recess and a second material layer is filled in the two contact holes respectively, and an anneal process is performed on the first material layer and the second material layer, to bend the two spacers into two inward curving spacers.

公开(公告)号：US20180350934A1

公开(公告)日：2018-12-06

申请号：US15613278

申请日：2017-06-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Rung-Yuan Lee ,  Chih-Wei Yang

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/40 ,  H01L29/66 ,  H01L29/10

Abstract: The present invention provides a method for forming a semiconductor structure, including the following steps: first, a substrate is provided, an interlayer dielectric (ILD) is formed on the substrate, a first dummy gate is formed in the ILD, wherein the first dummy gate includes a dummy gate electrode and two spacers disposed on two sides of the dummy gate electrode respectively. Next, two contact holes are formed in the ILD at two sides of the first dummy gate respectively. Afterwards, the dummy gate electrode is removed, so as to form a gate recess in the ILD, a first material layer is filled in the gate recess and a second material layer is filled in the two contact holes respectively, and an anneal process is performed on the first material layer and the second material layer, to bend the two spacers into two inward curving spacers.

公开(公告)号：US09673053B2

公开(公告)日：2017-06-06

申请号：US14549529

申请日：2014-11-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Rung-Yuan Lee ,  Yu-Ting Li ,  Jing-Yin Jhang ,  Chen-Yi Weng ,  Jia-Feng Fang ,  Yi-Wei Chen ,  Wei-Jen Wu ,  Po-Cheng Huang ,  Fu-Shou Tsai ,  Kun-Ju Li ,  Wen-Chin Lin ,  Chih-Chien Liu ,  Chih-Hsun Lin ,  Chun-Yuan Wu

IPC: H01L21/306 ,  H01L21/28

CPC classification number: H01L21/30625 ,  H01L21/28123 ,  H01L21/32115 ,  H01L21/3212

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first material layer on the substrate; forming a stop layer on the first material layer; forming a second material layer on the stop layer; and performing a planarizing process to remove the second material layer, the stop layer, and part of the first material layer for forming a gate layer.

公开(公告)号：US10475744B2

公开(公告)日：2019-11-12

申请号：US15727380

申请日：2017-10-06

Applicant: United Microelectronics Corp.

Inventor： Kuan-Hung Chen ,  Rung-Yuan Lee ,  Chun-Tsen Lu

IPC: H01L23/532 ,  H01L21/02 ,  H01L21/762 ,  H01L29/423 ,  H01L29/06 ,  B82Y99/00

Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a substrate, an isolation structure, an outer structure, and a gate structure. The isolation structure is disposed on the substrate. The outer structure surrounds a sidewall of the isolation structure. The gate structure surrounds a central part of the outer structure, so that the central part covered by the gate structure becomes a channel region, and the outer structure at both sides of the central part respectively becomes a source region and a drain region.

公开(公告)号：US20190081150A1

公开(公告)日：2019-03-14

申请号：US16178580

申请日：2018-11-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Rung-Yuan Lee ,  Chih-Wei Yang

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/423 ,  H01L29/10 ,  H01L29/40

CPC classification number: H01L29/49 ,  H01L29/41775 ,  H01L29/42376 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66606 ,  H01L29/7843

Abstract: The present invention provides a method for forming a semiconductor structure, including the following steps: first, a substrate is provided, an interlayer dielectric (ILD) is formed on the substrate, a first dummy gate is formed in the ILD, wherein the first dummy gate includes a dummy gate electrode and two spacers disposed on two sides of the dummy gate electrode respectively. Next, two contact holes are formed in the ILD at two sides of the first dummy gate respectively. Afterwards, the dummy gate electrode is removed, so as to form a gate recess in the ILD, a first material layer is filled in the gate recess and a second material layer is filled in the two contact holes respectively, and an anneal process is performed on the first material layer and the second material layer, to bend the two spacers into two inward curving spacers.

公开(公告)号：US20190074250A1

公开(公告)日：2019-03-07

申请号：US15727380

申请日：2017-10-06

Applicant: United Microelectronics Corp.

Inventor： Kuan-Hung Chen ,  Rung-Yuan Lee ,  Chun-Tsen Lu

IPC: H01L23/532 ,  H01L21/762 ,  H01L21/02

Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a substrate, an isolation structure, an outer structure, and a gate structure. The isolation structure is disposed on the substrate. The outer structure surrounds a sidewall of the isolation structure. The gate structure surrounds a central part of the outer structure, so that the central part covered by the gate structure becomes a channel region, and the outer structure at both sides of the central part respectively becomes a source region and a drain region.

公开(公告)号：US10396171B2

公开(公告)日：2019-08-27

申请号：US16178580

申请日：2018-11-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Rung-Yuan Lee ,  Chih-Wei Yang

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/51

Abstract: The present invention provides a method for forming a semiconductor structure, including the following steps: first, a substrate is provided, an interlayer dielectric (ILD) is formed on the substrate, a first dummy gate is formed in the ILD, wherein the first dummy gate includes a dummy gate electrode and two spacers disposed on two sides of the dummy gate electrode respectively. Next, two contact holes are formed in the ILD at two sides of the first dummy gate respectively. Afterwards, the dummy gate electrode is removed, so as to form a gate recess in the ILD, a first material layer is filled in the gate recess and a second material layer is filled in the two contact holes respectively, and an anneal process is performed on the first material layer and the second material layer, to bend the two spacers into two inward curving spacers.

公开(公告)号：US10043718B1

公开(公告)日：2018-08-07

申请号：US15672325

申请日：2017-08-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuan-Hung Chen ,  Rung-Yuan Lee ,  Chun-Tsen Lu ,  Chorng-Lih Young

IPC: H01L21/02 ,  H01L21/8238 ,  H01L21/20 ,  H01L21/225 ,  H01L29/16 ,  H01L21/8234 ,  H01L21/04 ,  H01L21/762 ,  H01L29/66 ,  H01L29/165 ,  H01L21/22 ,  H01L29/78

Abstract: A method of fabricating a semiconductor device includes the following steps: providing a semiconductor substrate having a fin structure thereon; forming a recess in the fin structure so that the semiconductor substrate is partially exposed from the bottom surface of the recess; forming a dopant source layer conformally disposed on side surfaces and a bottom surface of the recess; removing the dopant source layer disposed on the bottom surface of the recess until portions of the semiconductor substrate are exposed from the bottom surface of the recess; and annealing the dopant source layer so as to form a side doped region in the fin structure.