公开(公告)号：US10796964B2

公开(公告)日：2020-10-06

申请号：US16428651

申请日：2019-05-31

Applicant: United Microelectronics Corp.

Inventor： Shih-Yin Hsiao ,  Ching-Chung Yang ,  Kuan-Liang Liu

IPC: H01L29/06 ,  H01L27/02 ,  H01L21/8249 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/78 ,  H01L29/423

Abstract: A transistor structure includes a source region and a drain region disposed in a substrate, extending along a first direction. A polysilicon layer is disposed over the substrate, extending along a second direction perpendicular to the first direction, wherein the polysilicon layer includes a first edge region, a channel region and a second edge region formed as a gate region between the source region and the drain region in a plane view. The polysilicon layer has at least a first opening pattern at the first edge region having a first portion overlapping with the gate region; and at least a second opening pattern at the second edge region having a second portion overlapping with the gate region.

公开(公告)号：US20200212201A1

公开(公告)日：2020-07-02

申请号：US16813768

申请日：2020-03-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Kuan-Liang Liu ,  Ching-Chung Yang ,  Ping-Hung Chiang

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06

Abstract: A high voltage semiconductor device and a manufacturing method thereof are provided in the present invention. A recess is formed in a semiconductor substrate, and a gate dielectric layer and a main gate structure are formed in the recess. Therefore, the high voltage semiconductor device formed by the manufacturing method of the present invention may include the main gate structure lower than a top surface of an isolation structure formed in the semiconductor substrate. Problems about integrated manufacturing processes of the high voltage semiconductor device and other kinds of semiconductor devices when the gate structure is relatively high because of the thicker gate dielectric layer required in the high voltage semiconductor device may be improved accordingly.

公开(公告)号：US20190287860A1

公开(公告)日：2019-09-19

申请号：US16428651

申请日：2019-05-31

Applicant: United Microelectronics Corp.

Inventor： Shih-Yin Hsiao ,  Ching-Chung Yang ,  Kuan-Liang Liu

IPC: H01L21/8234 ,  H01L29/78 ,  H01L21/8249 ,  H01L29/49 ,  H01L27/02 ,  H01L29/06 ,  H01L29/423

Abstract: A transistor structure includes a source region and a drain region disposed in a substrate, extending along a first direction. A polysilicon layer is disposed over the substrate, extending along a second direction perpendicular to the first direction, wherein the polysilicon layer includes a first edge region, a channel region and a second edge region formed as a gate region between the source region and the drain region in a plane view. The polysilicon layer has at least a first opening pattern at the first edge region having a first portion overlapping with the gate region; and at least a second opening pattern at the second edge region having a second portion overlapping with the gate region.

公开(公告)号：US20170243950A1

公开(公告)日：2017-08-24

申请号：US15047644

申请日：2016-02-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuan-Liang Liu ,  Shih-Yin Hsiao ,  Ching-Chung Yang

IPC: H01L29/66 ,  H01L21/223

CPC classification number: H01L29/66598 ,  H01L21/26513 ,  H01L29/7833

Abstract: A method of fabricating a transistor with reduced hot carrier injection effects includes providing a substrate covered by a gate material layer. Later, the gate material layer is patterned into a gate electrode. Then, a mask layer is formed to cover part of the gate electrode and expose two ends of the gate electrode. Finally, a first implantation process is performed to implant dopants through the exposed two ends of the gate electrode into the substrate directly under the gate electrode to form two LDD regions by taking the mask layer as a mask.

公开(公告)号：US20170186652A1

公开(公告)日：2017-06-29

申请号：US14980779

申请日：2015-12-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Kuan-Liang Liu

IPC: H01L21/8234 ,  H01L29/49 ,  H01L27/088 ,  H01L21/3105 ,  H01L21/02 ,  H01L29/40 ,  H01L21/311

CPC classification number: H01L21/823481 ,  H01L21/0217 ,  H01L21/31053 ,  H01L21/31105 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/401 ,  H01L29/4966

Abstract: A method for manufacturing a semiconductor device and a device manufactured using the same are provided. According to a method approach of the embodiment, a substrate having at least a first area with a plurality of polysilicon gates and a second area adjacent to the first area is provided. A contact etch stop layer (CESL) over the polysilicon gates of the first area is formed, and the CESL extends to the second area. Then, a dielectric layer is formed on the CESL, and a nitride layer is formed on the dielectric layer. The nitride layer is patterned to expose the dielectric layer in the first area and to form a pattern of dummy nitrides on the dielectric layer in the second area.

公开(公告)号：US09647060B2

公开(公告)日：2017-05-09

申请号：US14859348

申请日：2015-09-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Kuan-Liang Liu

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L29/7836

Abstract: A method for fabricating isolation device is disclosed. The method includes the steps of: providing a substrate; forming a shallow trench isolation (STI) in the substrate, the STI includes a first STI and a second STI, and the first STI surrounds a first device region and the second STI surrounds a second device region; forming a first doped region between and contact the first STI and the second STI; and forming a first gate structure on the first doped region, the first STI and the second STI.

公开(公告)号：US20250040227A1

公开(公告)日：2025-01-30

申请号：US18237401

申请日：2023-08-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuan-Liang Liu ,  Szu-Han Huang

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: A semiconductor device includes a gate structure, an insulating layer and two source/drain regions. A portion of the gate structure is embedded in a substrate. The insulating layer is disposed between the portion of the gate structure and the substrate and encompasses the portion of the gate structure. The two source/drain regions are disposed in the substrate and respectively located at two sides of the gate structure.

公开(公告)号：US12087635B2

公开(公告)日：2024-09-10

申请号：US18335154

申请日：2023-06-15

Applicant: United Microelectronics Corp.

Inventor： Shih-Yin Hsiao ,  Ching-Chung Yang ,  Kuan-Liang Liu

IPC: H01L27/02 ,  H01L21/8234 ,  H01L21/8249 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L21/823425 ,  H01L21/823437 ,  H01L21/8249 ,  H01L27/0251 ,  H01L29/0607 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4925 ,  H01L29/7832 ,  H01L29/7835 ,  H01L29/78

Abstract: A transistor structure includes a source region and a drain region disposed in a substrate, extending along a first direction. A polysilicon layer is disposed over the substrate, extending along a second direction perpendicular to the first direction, wherein the polysilicon layer includes a first edge region, a channel region and a second edge region formed as a gate region between the source region and the drain region. The polysilicon layer has at least a first opening pattern at the first edge region having a first portion overlapping the gate region; and at least a second opening pattern at the second edge region having a second portion overlapping the gate region.

公开(公告)号：US11721587B2

公开(公告)日：2023-08-08

申请号：US17367150

申请日：2021-07-02

Applicant: United Microelectronics Corp.

Inventor： Shih-Yin Hsiao ,  Ching-Chung Yang ,  Kuan-Liang Liu

IPC: H01L29/06 ,  H01L27/02 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/78 ,  H01L21/8249 ,  H01L29/423

CPC classification number: H01L21/823425 ,  H01L21/8249 ,  H01L21/823437 ,  H01L27/0251 ,  H01L29/0607 ,  H01L29/4238 ,  H01L29/42368 ,  H01L29/4925 ,  H01L29/7832 ,  H01L29/7835 ,  H01L29/78

Abstract: A transistor structure includes a source region and a drain region disposed in a substrate, extending along a first direction. A polysilicon layer is disposed over the substrate, extending along a second direction perpendicular to the first direction, wherein the polysilicon layer includes a first edge region, a channel region and a second edge region formed as a gate region between the source region and the drain region. The polysilicon layer has at least a first opening pattern at the first edge region having a first portion overlapping the gate region; and at least a second opening pattern at the second edge region having a second portion overlapping the gate region.

公开(公告)号：US10373876B2

公开(公告)日：2019-08-06

申请号：US15953537

申请日：2018-04-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Kuan-Liang Liu

IPC: H01L21/8234 ,  H01L29/40 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/02 ,  H01L27/088 ,  H01L29/49

Abstract: A method for manufacturing a semiconductor device and a device manufactured using the same are provided. According to a method approach of the embodiment, a substrate having at least a first area with a plurality of polysilicon gates and a second area adjacent to the first area is provided. A contact etch stop layer (CESL) over the polysilicon gates of the first area is formed, and the CESL extends to the second area. Then, a dielectric layer is formed on the CESL, and a nitride layer is formed on the dielectric layer. The nitride layer is patterned to expose the dielectric layer in the first area and to form a pattern of dummy nitrides on the dielectric layer in the second area.