公开(公告)号：US20160329276A1

公开(公告)日：2016-11-10

申请号：US14859367

申请日：2015-09-21

Applicant: United Microelectronics Corp.

Inventor： Shih-Chin Lin ,  Kuei-Chun Hung ,  Jerry CHE JEN HU ,  Ming-Jui Chen ,  Chen-Hsien Hsu

IPC: H01L23/528 ,  H01L27/088 ,  H01L27/115 ,  H01L23/522 ,  H01L23/00 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/0924 ,  H01L21/28518 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/4983 ,  H01L29/785 ,  H01L2224/48132 ,  H01L2924/00014 ,  H01L2924/37001 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A semiconductor integrated circuit layout structure includes a first active region, a second active region isolating from the first active region, a gate structure straddling the first active region and the second active region, and a plurality of conductive structures. The first active region at two opposite sides of the gate structure respectively forms a first source region and a first drain region. The second active region at two opposite sides of the gate structure respectively forms a second source region and a second drain region. The conductive structures include a plurality of slot-type conductive structures and one island-type conductive structure. The slot-type conductive structures are respectively formed on the first source region, the first drain region, the second source region and the second drain region. The island-type conductive structure is formed on the gate structure.

Abstract translation: 半导体集成电路布局结构包括第一有源区，与第一有源区隔离的第二有源区，跨过第一有源区和第二有源区的栅极结构以及多个导电结构。 栅极结构的两个相对侧的第一有源区分别形成第一源极区域和第一漏极区域。 栅极结构的两个相对侧的第二有源区分别形成第二源极区和第二漏极区。 导电结构包括多个槽型导电结构和一个岛型导电结构。 槽型导电结构分别形成在第一源极区域，第一漏极区域，第二源极区域和第二漏极区域上。 岛型导电结构形成在栅极结构上。

公开(公告)号：US09007571B2

公开(公告)日：2015-04-14

申请号：US13971776

申请日：2013-08-20

Applicant: United Microelectronics Corp.

Inventor： Wei-Jhe Tzai ,  Kuei-Chun Hung ,  Chun-Chi Yu ,  Chien-Hao Chen ,  Chia-Ching Lin

IPC: G01N21/00 ,  G03F9/00

CPC classification number: G03F7/70633

Abstract: A measurement method of an overlay mark is provided. An overlay mark on a wafer is measured with a plurality of different wavelength regions of an optical measurement tool, so as to obtain a plurality of overlay values corresponding to the wavelength regions. The overlay mark on the wafer is measured with an electrical measurement tool to obtain a reference overlay value. The wavelength region that corresponds to the overlay value closest to the reference overlay value is determined as a correct wavelength region for the overlay mark.

Abstract translation: 提供重叠标记的测量方法。 用光学测量工具的多个不同波长区域测量晶片上的覆盖标记，以便获得对应于波长区域的多个覆盖值。 用电测量工具测量晶片上的覆盖标记以获得参考覆盖值。 对应于最接近参考叠加值的覆盖值的波长区域被确定为覆盖标记的正确波长区域。

公开(公告)号：US20150055125A1

公开(公告)日：2015-02-26

申请号：US13971776

申请日：2013-08-20

Applicant: United Microelectronics Corp.

Inventor： Wei-Jhe Tzai ,  Kuei-Chun Hung ,  Chun-Chi Yu ,  Chien-Hao Chen ,  Chia-Ching Lin

IPC: G03F9/00

CPC classification number: G03F7/70633

Abstract: A measurement method of an overlay mark is provided. An overlay mark on a wafer is measured with a plurality of different wavelength regions of an optical measurement tool, so as to obtain a plurality of overlay values corresponding to the wavelength regions. The overlay mark on the wafer is measured with an electrical measurement tool to obtain a reference overlay value. The wavelength region that corresponds to the overlay value closest to the reference overlay value is determined as a correct wavelength region for the overlay mark.

Abstract translation: 提供重叠标记的测量方法。 用光学测量工具的多个不同波长区域测量晶片上的覆盖标记，以便获得对应于波长区域的多个覆盖值。 用电测量工具测量晶片上的覆盖标记以获得参考覆盖值。 对应于最接近参考叠加值的覆盖值的波长区域被确定为覆盖标记的正确波长区域。