公开(公告)号：US20160103396A1

公开(公告)日：2016-04-14

申请号：US14512484

申请日：2014-10-13

申请人： UNITED MICROELECTRONICS CORP.

发明人： En-Chiuan Liou ,  Teng-Chin Kuo ,  Chun-Chi Yu

IPC分类号： G03F7/20

CPC分类号： G03F7/70058 ,  G03F7/70466 ,  G03F7/70625

摘要： A double patterning method comprises the following steps. First of all, a target layer and a mask layer stacked thereon are provided. Next, a first pattern opening is formed in the mask layer, and a width of the first pattern opening is measured to obtain a measuring value. Then, a second pattern opening is formed in the mask layer based on the measuring value, wherein the second pattern opening and the first pattern opening are co-planar. Finally, a bias trimming process is performed to trim the first pattern opening and the second pattern opening.

摘要翻译： 双重图案化方法包括以下步骤。 首先，提供堆叠在其上的目标层和掩模层。 接下来，在掩模层中形成第一图案开口，并且测量第一图案开口的宽度以获得测量值。 然后，基于测量值在掩模层中形成第二图案开口，其中第二图案开口和第一图案开口是共面的。 最后，执行偏置修剪处理以修剪第一图案开口和第二图案开口。

公开(公告)号：US20150293461A1

公开(公告)日：2015-10-15

申请号：US14279039

申请日：2014-05-15

申请人： United Microelectronics Corp.

发明人： En-Chiuan Liou ,  Chia-Chang Hsu ,  Yi-Ting Chen ,  Teng-Chin Kuo ,  Chun-Chi Yu

IPC分类号： G03F7/20

CPC分类号： G03F7/70516

摘要： An overlap mark set is provided to have at least a first and a second overlap marks both of which are located at the same pattern layer. The first overlap mark includes at least two sets of X-directional linear patterns, having a preset offset a1 therebetween; and at least two sets of Y-directional linear patterns, having the preset offset a1 therebetween. The second overlap mark includes at least two sets of X-directional linear patterns, having a preset offset b1 therebetween; and at least two sets of Y-directional linear patterns, having the preset offset b1 therebetween. The preset offsets a1 and b1 are not equal.

摘要翻译： 提供重叠标记集以具有两个位于相同图案层的至少第一和第二重叠标记。 第一重叠标记包括至少两组X方向线性图案，其间具有预置偏移量a1; 以及至少两组Y方向线性图案，其间具有预设偏移量a1。 第二重叠标记包括至少两组X方向线性图案，其间具有预设偏移量b1; 以及至少两组Y方向线性图案，其间具有预设偏移量b1。 预置偏移量a1和b1不相等。

公开(公告)号：US09147601B2

公开(公告)日：2015-09-29

申请号：US14541148

申请日：2014-11-14

申请人： UNITED MICROELECTRONICS CORP.

发明人： Cheng-Han Wu ,  Chun-Chi Yu

IPC分类号： H01L21/311 ,  H01L21/302 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/033 ,  H01L21/027

CPC分类号： H01L21/76816 ,  H01L21/0276 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/32139

摘要： The present invention provides a method of forming via holes. First, a substrate is provided. A plurality of first areas is defined on the substrate. A dielectric layer and a blocking layer are formed on the substrate. A patterned layer is formed on the blocking layer such that a sidewall of the blocking layer is completely covered by the patterned layer. The patterned layer includes a plurality of holes arranged in a regular array wherein the area of the hole array is greater than those of the first areas. The blocking layer in the first areas is removed by using the patterned layer as a mask. Lastly, the dielectric layer is patterned to form at least a via hole in the dielectric layer in the first area.

摘要翻译： 本发明提供一种形成通孔的方法。 首先，提供基板。 在基板上限定多个第一区域。 在基板上形成介电层和阻挡层。 在阻挡层上形成图案层，使得阻挡层的侧壁被图案化层完全覆盖。 图案化层包括以规则阵列布置的多个孔，其中孔阵列的面积大于第一区域的面积。 通过使用图案化层作为掩模来去除第一区域中的阻挡层。 最后，电介质层被图案化以在第一区域中的电介质层中至少形成通孔。

公开(公告)号：US09007571B2

公开(公告)日：2015-04-14

申请号：US13971776

申请日：2013-08-20

申请人： United Microelectronics Corp.

发明人： Wei-Jhe Tzai ,  Kuei-Chun Hung ,  Chun-Chi Yu ,  Chien-Hao Chen ,  Chia-Ching Lin

IPC分类号： G01N21/00 ,  G03F9/00

CPC分类号： G03F7/70633

摘要： A measurement method of an overlay mark is provided. An overlay mark on a wafer is measured with a plurality of different wavelength regions of an optical measurement tool, so as to obtain a plurality of overlay values corresponding to the wavelength regions. The overlay mark on the wafer is measured with an electrical measurement tool to obtain a reference overlay value. The wavelength region that corresponds to the overlay value closest to the reference overlay value is determined as a correct wavelength region for the overlay mark.

摘要翻译： 提供重叠标记的测量方法。 用光学测量工具的多个不同波长区域测量晶片上的覆盖标记，以便获得对应于波长区域的多个覆盖值。 用电测量工具测量晶片上的覆盖标记以获得参考覆盖值。 对应于最接近参考叠加值的覆盖值的波长区域被确定为覆盖标记的正确波长区域。

公开(公告)号：US20150072529A1

公开(公告)日：2015-03-12

申请号：US14541148

申请日：2014-11-14

申请人： UNITED MICROELECTRONICS CORP.

发明人： Cheng-Han Wu ,  Chun-Chi Yu

IPC分类号： H01L21/768 ,  H01L21/311 ,  H01L21/027

CPC分类号： H01L21/76816 ,  H01L21/0276 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/32139

摘要： The present invention provides a method of forming via holes. First, a substrate is provided. A plurality of first areas is defined on the substrate. A dielectric layer and a blocking layer are formed on the substrate. A patterned layer is formed on the blocking layer such that a sidewall of the blocking layer is completely covered by the patterned layer. The patterned layer includes a plurality of holes arranged in a regular array wherein the area of the hole array is greater than those of the first areas. The blocking layer in the first areas is removed by using the patterned layer as a mask. Lastly, the dielectric layer is patterned to form at least a via hole in the dielectric layer in the first area.

摘要翻译： 本发明提供一种形成通孔的方法。 首先，提供基板。 在基板上限定多个第一区域。 在基板上形成介电层和阻挡层。 在阻挡层上形成图案层，使得阻挡层的侧壁被图案化层完全覆盖。 图案化层包括以规则阵列布置的多个孔，其中孔阵列的面积大于第一区域的面积。 通过使用图案化层作为掩模来去除第一区域中的阻挡层。 最后，电介质层被图案化以在第一区域中的电介质层中至少形成通孔。

公开(公告)号：US20150055125A1

公开(公告)日：2015-02-26

申请号：US13971776

申请日：2013-08-20

申请人： United Microelectronics Corp.

发明人： Wei-Jhe Tzai ,  Kuei-Chun Hung ,  Chun-Chi Yu ,  Chien-Hao Chen ,  Chia-Ching Lin

IPC分类号： G03F9/00

CPC分类号： G03F7/70633

摘要： A measurement method of an overlay mark is provided. An overlay mark on a wafer is measured with a plurality of different wavelength regions of an optical measurement tool, so as to obtain a plurality of overlay values corresponding to the wavelength regions. The overlay mark on the wafer is measured with an electrical measurement tool to obtain a reference overlay value. The wavelength region that corresponds to the overlay value closest to the reference overlay value is determined as a correct wavelength region for the overlay mark.

摘要翻译： 提供重叠标记的测量方法。 用光学测量工具的多个不同波长区域测量晶片上的覆盖标记，以便获得对应于波长区域的多个覆盖值。 用电测量工具测量晶片上的覆盖标记以获得参考覆盖值。 对应于最接近参考叠加值的覆盖值的波长区域被确定为覆盖标记的正确波长区域。

公开(公告)号：US12106962B2

公开(公告)日：2024-10-01

申请号：US17341183

申请日：2021-06-07

申请人： United Microelectronics Corp.

发明人： Yi Jing Wang ,  Chia-Chang Hsu ,  Chien-Hao Chen ,  Chang-Mao Wang ,  Chun-Chi Yu

IPC分类号： H01L21/033 ,  G03F7/00 ,  G03F7/20 ,  H01L21/311 ,  H01L21/66 ,  H01L23/544

CPC分类号： H01L21/0337 ,  G03F7/2022 ,  G03F7/70633 ,  H01L21/31144 ,  H01L22/20 ,  H01L23/544

摘要： The embodiments of the disclosure provide a patterning method, which includes the following processes. A target layer is formed on a substrate. A hard mask layer is formed over the target layer. A first patterning process is performed on the hard mask layer by using a photomask having a first pattern with a first pitch. The photomask is shifted along a first direction by a first distance. A second patterning process is performed on the hard mask layer by using the photomask that has been shifted, so as to form a patterned hard mask. The target layer is patterned using the patterned hard mask to form a patterned target layer. The target layer has a second pattern with a second pitch less than the first pitch.

公开(公告)号：US20230402288A1

公开(公告)日：2023-12-14

申请号：US17857158

申请日：2022-07-04

申请人： UNITED MICROELECTRONICS CORP.

发明人： Yeh-Sheng Lin ,  Chang-Mao Wang ,  Chun-Chi Yu ,  Chung-Yi Chiu

IPC分类号： H01L21/311 ,  H01L21/768

CPC分类号： H01L21/31111 ,  H01L21/76802 ,  H01L21/31144

摘要： A method of removing a step height on a gate structure includes providing a substrate. A gate structure is disposed on the substrate. A dielectric layer covers the gate structure and the substrate. Then, a composite material layer is formed to cover the dielectric layer. Later, part of the composite material layer is removed to form a step height disposed directly on the gate structure. Subsequently, a wet etching is performed to remove the step height. After the step height is removed, the dielectric layer is etched to form a first contact hole to expose the gate structure.

公开(公告)号：US10916636B2

公开(公告)日：2021-02-09

申请号：US16276642

申请日：2019-02-15

申请人： UNITED MICROELECTRONICS CORP.

发明人： Po-Tsang Chen ,  Wen-Liang Huang ,  Chun-Chi Yu

IPC分类号： H01L29/66 ,  H01L21/28 ,  H01L21/027 ,  H01L29/49

摘要： A method of forming gates includes the following steps. Dummy gates are formed on a substrate. A spacer material is deposited to conformally cover the dummy gates. A removing process is performed to remove parts of the spacer material and the dummy gates, thereby forming spacers and recesses in the spacers.

公开(公告)号：US09482964B2

公开(公告)日：2016-11-01

申请号：US14279039

申请日：2014-05-15

申请人： United Microelectronics Corp.

发明人： En-Chiuan Liou ,  Chia-Chang Hsu ,  Yi-Ting Chen ,  Teng-Chin Kuo ,  Chun-Chi Yu

IPC分类号： G03F7/20

CPC分类号： G03F7/70516

摘要： An overlap mark set is provided to have at least a first and a second overlap marks both of which are located at the same pattern layer. The first overlap mark includes at least two sets of X-directional linear patterns, having a preset offset a1 therebetween; and at least two sets of Y-directional linear patterns, having the preset offset a1 therebetween. The second overlap mark includes at least two sets of X-directional linear patterns, having a preset offset b1 therebetween; and at least two sets of Y-directional linear patterns, having the preset offset b1 therebetween. The preset offsets a1 and b1 are not equal.

摘要翻译： 提供重叠标记集以具有两个位于相同图案层的至少第一和第二重叠标记。 第一重叠标记包括至少两组X方向线性图案，其间具有预置偏移量a1; 以及至少两组Y方向线性图案，其间具有预设偏移量a1。 第二重叠标记包括至少两组X方向线性图案，其间具有预设偏移量b1; 以及至少两组Y方向线性图案，其间具有预设的偏移量b1。 预置偏移量a1和b1不相等。