公开(公告)号：US20160314233A1

公开(公告)日：2016-10-27

申请号：US14692723

申请日：2015-04-21

Applicant: United Microelectronics Corp.

Inventor： Harn-Jiunn Wang ,  Kuei-Chun Hung ,  Chih-Hsien Tang ,  Chin-Lung Lin

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G03F1/70 ,  G03F7/70433 ,  G03F7/70466

Abstract: A method of decomposing pattern layout for generating patterns on photomasks is disclosed. The method includes decomposing features of an integrated circuit layout into discrete patterns based on the relation between these features. The features include first features and second features. The first features are then classified into a first feature pattern and a second feature pattern, and the second features are classified into third, fourth, fifth and sixth feature patterns. The spacings of the second features in the fifth and sixth feature patterns are greater than a minimum exposure limits. Finally, the first feature pattern is outputted to a first photomask, the second feature pattern is outputted to a second photomask, the third and fifth feature patterns are outputted to a third photomask, and the fourth and sixth feature patterns are outputted to a fourth photomask.

Abstract translation: 公开了一种分解用于在光掩模上产生图案的图案布局的方法。 该方法包括基于这些特征之间的关系将集成电路布局的特征分解为离散模式。 功能包括第一个功能和第二个功能。 然后将第一特征分类为第一特征图案和第二特征图案，并且将第二特征分类为第三，第四，第五和第六特征图案。 第五和第六特征图案中的第二特征的间距大于最小暴露极限。 最后，将第一特征图案输出到第一光掩模，将第二特征图案输出到第二光掩模，将第三和第五特征图案输出到第三光掩模，并将第四和第六特征图案输出到第四光掩模 。

公开(公告)号：US09524362B2

公开(公告)日：2016-12-20

申请号：US14692723

申请日：2015-04-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Harn-Jiunn Wang ,  Kuei-Chun Hung ,  Chih-Hsien Tang ,  Chin-Lung Lin

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G03F1/70 ,  G03F7/70433 ,  G03F7/70466

Abstract: A method of decomposing pattern layout for generating patterns on photomasks is disclosed. The method includes decomposing features of an integrated circuit layout into discrete patterns based on the relation between these features. The features include first features and second features. The first features are then classified into a first feature pattern and a second feature pattern, and the second features are classified into third, fourth, fifth and sixth feature patterns. The spacings of the second features in the fifth and sixth feature patterns are greater than a minimum exposure limits. Finally, the first feature pattern is outputted to a first photomask, the second feature pattern is outputted to a second photomask, the third and fifth feature patterns are outputted to a third photomask, and the fourth and sixth feature patterns are outputted to a fourth photomask.

Abstract translation: 公开了一种分解用于在光掩模上产生图案的图案布局的方法。 该方法包括基于这些特征之间的关系将集成电路布局的特征分解为离散模式。 功能包括第一个功能和第二个功能。 然后将第一特征分类为第一特征图案和第二特征图案，并且将第二特征分类为第三，第四，第五和第六特征图案。 第五和第六特征图案中的第二特征的间距大于最小暴露极限。 最后，将第一特征图案输出到第一光掩模，将第二特征图案输出到第二光掩模，将第三和第五特征图案输出到第三光掩模，并将第四和第六特征图案输出到第四光掩模 。

公开(公告)号：US20170221897A1

公开(公告)日：2017-08-03

申请号：US15484126

申请日：2017-04-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Chin Lin ,  Kuei-Chun Hung ,  Jerry CHE JEN HU ,  Ming-Jui Chen ,  Chen-Hsien Hsu

IPC: H01L27/092 ,  H01L23/528 ,  H01L27/088 ,  H01L23/522 ,  H01L27/02 ,  H01L29/06

CPC classification number: H01L27/0924 ,  H01L21/28518 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/4983 ,  H01L29/785 ,  H01L2224/48132 ,  H01L2924/00014 ,  H01L2924/37001 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A semiconductor IC layout structure includes a plurality of first active regions arranged along a second direction, a plurality of second active regions arranged along the second direction, a plurality of gate structures extending along a first direction and respectively straddling the first active regions and the second active regions, a plurality of first conductive structures extending along the first direction, and a plurality of second conductive structures formed on the gate structures. The second active regions are isolated from the first active regions. The first direction is perpendicular to the second direction. The first conductive structures are formed on the first active regions and the second active regions. The second conductive structures include a plurality of slot-type second conductive structures extended along the second direction and a plurality of island-type second conductive structures formed on the gate structures.

公开(公告)号：US09653346B2

公开(公告)日：2017-05-16

申请号：US14800697

申请日：2015-07-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Chin Lin ,  Kuei-Chun Hung ,  Jerry Che Jen Hu ,  Ming-Jui Chen ,  Chen-Hsien Hsu

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L29/78 ,  H01L23/535

CPC classification number: H01L21/76816 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L29/7851

Abstract: An integrated circuits structure includes a semiconductor substrate, at least an non-planar field effect transistor (FET) device formed on the semiconductor substrate, and an interconnection structure formed on the semiconductor substrate. The non-planar FET device includes a plurality of fins and a gate electrode. The interconnection structure includes a plurality of first group metals and a plurality of second group metals. The first group metals are formed on the non-planar FET and the second group metals are formed on the first group metals. The first group metals include a first metal pitch and the second group metals include a second metal pitch. The second metal pitch is 1.2-1.5 times to the first metal pitch.

公开(公告)号：US20150276382A1

公开(公告)日：2015-10-01

申请号：US14226834

申请日：2014-03-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Kuei-Chun Hung ,  Chun-Chi Yu

IPC: G01B11/14 ,  G01B11/28

CPC classification number: G03F9/7076

Abstract: A measurement mark structure includes a mark pattern and a pair of assistant bars positioned at two opposite sides of the mark pattern. The mark pattern includes a plurality of segments. The segments of the mark pattern are arranged along a first direction and the pair of the assistant bars are expend along the first direction.

Abstract translation: 测量标记结构包括标记图案和位于标记图案的两个相对侧的一对辅助条。 标记图案包括多个片段。 标记图案的区段沿着第一方向布置，并且一对辅助条沿着第一方向消耗。

公开(公告)号：US11482517B2

公开(公告)日：2022-10-25

申请号：US15980759

申请日：2018-05-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chih-Wei Yang ,  Kuei-Chun Hung

IPC: H01L27/02 ,  H01L21/3213 ,  H01L27/11582 ,  H01L49/02

Abstract: An integrated circuit process includes the following steps. A substrate including a first area and a second area is provided. A plurality of line patterns cover the substrate of the first area, and a sacrificial line pattern covers the substrate of the second area, wherein these line patterns separate from and are orthogonal to the sacrificial line pattern. The present invention also provides an integrated circuit formed by said process. A substrate includes a first area and a second area; a plurality of line patterns cover the substrate of the first area; a slot pattern is in the substrate of the second area, wherein these line patterns are orthogonal to the slot pattern. Additionally, a plurality of line patterns cover the substrate; a sacrificial line pattern is at ends of the line patterns, wherein these line patterns separate from and are orthogonal to the sacrificial line pattern.

公开(公告)号：US20180261589A1

公开(公告)日：2018-09-13

申请号：US15980759

申请日：2018-05-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chih-Wei Yang ,  Kuei-Chun Hung

IPC: H01L27/02 ,  H01L27/11582 ,  H01L21/3213

CPC classification number: H01L27/0207 ,  H01L21/32139 ,  H01L27/11582 ,  H01L28/00

Abstract: An integrated circuit process includes the following steps. A substrate including a first area and a second area is provided. A plurality of line patterns cover the substrate of the first area, and a sacrificial line pattern covers the substrate of the second area, wherein these line patterns separate from and are orthogonal to the sacrificial line pattern. The present invention also provides an integrated circuit formed by said process. A substrate includes a first area and a second area; a plurality of line patterns cover the substrate of the first area; a slot pattern is in the substrate of the second area, wherein these line patterns are orthogonal to the slot pattern. Additionally, a plurality of line patterns cover the substrate; a sacrificial line pattern is at ends of the line patterns, wherein these line patterns separate from and are orthogonal to the sacrificial line pattern.

公开(公告)号：US09905562B2

公开(公告)日：2018-02-27

申请号：US15484126

申请日：2017-04-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Chin Lin ,  Kuei-Chun Hung ,  Jerry Che Jen Hu ,  Ming-Jui Chen ,  Chen-Hsien Hsu

IPC: H01L27/118 ,  H01L27/092 ,  H01L27/02 ,  H01L29/06 ,  H01L27/088 ,  H01L23/522 ,  H01L23/528 ,  H01L21/285 ,  H01L21/8238 ,  H01L29/49

CPC classification number: H01L27/0924 ,  H01L21/28518 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/4983 ,  H01L29/785 ,  H01L2224/48132 ,  H01L2924/00014 ,  H01L2924/37001 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A semiconductor IC layout structure includes a plurality of first active regions arranged along a second direction, a plurality of second active regions arranged along the second direction, a plurality of gate structures extending along a first direction and respectively straddling the first active regions and the second active regions, a plurality of first conductive structures extending along the first direction, and a plurality of second conductive structures formed on the gate structures. The second active regions are isolated from the first active regions. The first direction is perpendicular to the second direction. The first conductive structures are formed on the first active regions and the second active regions. The second conductive structures include a plurality of slot-type second conductive structures extended along the second direction and a plurality of island-type second conductive structures formed on the gate structures.

公开(公告)号：US09673145B2

公开(公告)日：2017-06-06

申请号：US14859367

申请日：2015-09-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Chin Lin ,  Kuei-Chun Hung ,  Jerry Che Jen Hu ,  Ming-Jui Chen ,  Chen-Hsien Hsu

IPC: H01L29/82 ,  H01L23/528 ,  H01L29/78 ,  H01L29/06 ,  H01L23/522 ,  H01L23/00 ,  H01L27/02 ,  H01L27/118

CPC classification number: H01L27/0924 ,  H01L21/28518 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/4983 ,  H01L29/785 ,  H01L2224/48132 ,  H01L2924/00014 ,  H01L2924/37001 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A semiconductor integrated circuit layout structure includes a first active region, a second active region isolating from the first active region, a gate structure straddling the first active region and the second active region, and a plurality of conductive structures. The first active region at two opposite sides of the gate structure respectively forms a first source region and a first drain region. The second active region at two opposite sides of the gate structure respectively forms a second source region and a second drain region. The conductive structures include a plurality of slot-type conductive structures and one island-type conductive structure. The slot-type conductive structures are respectively formed on the first source region, the first drain region, the second source region and the second drain region. The island-type conductive structure is formed on the gate structure.

公开(公告)号：US20170117151A1

公开(公告)日：2017-04-27

申请号：US14945443

申请日：2015-11-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chih-Wei Yang ,  Kuei-Chun Hung

IPC: H01L21/033 ,  H01L27/02

CPC classification number: H01L27/0207 ,  H01L21/32139 ,  H01L27/11582 ,  H01L28/00

Abstract: An integrated circuit process includes the following steps. A substrate including a first area and a second area is provided. A plurality of line patterns cover the substrate of the first area, and a sacrificial line pattern covers the substrate of the second area, wherein these line patterns separate from and are orthogonal to the sacrificial line pattern. The present invention also provides an integrated circuit formed by said process. A substrate includes a first area and a second area; a plurality of line patterns cover the substrate of the first area; a slot pattern is in the substrate of the second area, wherein these line patterns are orthogonal to the slot pattern. Additionally, a plurality of line patterns cover the substrate; a sacrificial line pattern is at ends of the line patterns, wherein these line patterns separate from and are orthogonal to the sacrificial line pattern.