公开(公告)号：US20160111509A1

公开(公告)日：2016-04-21

申请号：US14519153

申请日：2014-10-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Huang Yu ,  Shih-Yin Hsiao

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/66545 ,  H01L21/76895 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/401 ,  H01L29/402 ,  H01L29/4238 ,  H01L29/66568 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7835

Abstract: A MOS transistor device includes a substrate including a gate formed thereon, and a spacer being formed on a sidewall of the gate; a source region and a drain region formed in the substrate; and at least a first dummy contact formed above the substrate on a drain side of the gate. More important, the first dummy contact is formed apart from a surface of the substrate.

Abstract translation: MOS晶体管器件包括其上形成有栅极的衬底和形成在栅极的侧壁上的间隔物; 形成在所述基板中的源极区域和漏极区域; 以及形成在栅极的漏极侧的衬底上方的至少第一虚拟接触。 更重要的是，第一虚拟接触件与衬底的表面分开形成。

公开(公告)号：US20160043193A1

公开(公告)日：2016-02-11

申请号：US14882462

申请日：2015-10-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Huang Yu ,  Shih-Yin Hsiao ,  Wen-Fang Lee ,  Shu-Wen Lin ,  Kuan-Chuan Chen

IPC: H01L29/423 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/42368 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/28026 ,  H01L21/28158 ,  H01L21/2822 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/401 ,  H01L29/6659 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7834

Abstract: The present invention provides a high-voltage metal-oxide-semiconductor (HVMOS) transistor comprising a substrate, a gate dielectric layer, a gate electrode and a source and drain region. The gate dielectric layer is disposed on the substrate and includes a protruded portion and a recessed portion, wherein the protruded portion is disposed adjacent to two sides of the recessed portion and has a thickness greater than a thickness of the recessed portion. The gate electrode is disposed on the gate dielectric layer. Thus, the protruded portion of the gate dielectric layer can maintain a higher breakdown voltage, thereby keeping the current from leaking through the gate.

Abstract translation: 本发明提供一种高压金属氧化物半导体（HVMOS）晶体管，其包括衬底，栅极电介质层，栅极电极和源极和漏极区域。 栅介质层设置在基板上，并且包括突出部分和凹陷部分，其中突出部分邻近凹部的两侧设置，并且具有大于凹部的厚度的厚度。 栅电极设置在栅介质层上。 因此，栅极电介质层的突出部分可以保持更高的击穿电压，从而保持电流不通过栅极泄漏。

公开(公告)号：US20150287797A1

公开(公告)日：2015-10-08

申请号：US14273538

申请日：2014-05-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Huang Yu ,  Shih-Yin Hsiao ,  Wen-Fang Lee ,  Shu-Wen Lin ,  Kuan-Chuan Chen

IPC: H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L29/08 ,  H01L21/266 ,  H01L29/78 ,  H01L29/40

CPC classification number: H01L29/42368 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/28026 ,  H01L21/28158 ,  H01L21/2822 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/401 ,  H01L29/6659 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7834

Abstract: The present invention provides a high-voltage metal-oxide-semiconductor (HVMOS) transistor comprising a substrate, a gate dielectric layer, a gate electrode and a source and drain region. The gate dielectric layer is disposed on the substrate and includes a protruded portion and a recessed portion, wherein the protruded portion is disposed adjacent to two sides of the recessed portion and has a thickness greater than a thickness of the recessed portion. The gate electrode is disposed on the gate dielectric layer. Thus, the protruded portion of the gate dielectric layer can maintain a higher breakdown voltage, thereby keeping the current from leaking through the gate.

Abstract translation: 本发明提供一种高压金属氧化物半导体（HVMOS）晶体管，其包括衬底，栅极电介质层，栅极电极和源极和漏极区域。 栅介质层设置在基板上，并且包括突出部分和凹陷部分，其中突出部分邻近凹部的两侧设置，并且具有大于凹部的厚度的厚度。 栅电极设置在栅介质层上。 因此，栅极电介质层的突出部分可以保持更高的击穿电压，从而保持电流不通过栅极泄漏。

公开(公告)号：US09812327B2

公开(公告)日：2017-11-07

申请号：US14863177

申请日：2015-09-23

Applicant: United Microelectronics Corp.

Inventor： Kun-Huang Yu ,  Shih-Yin Hsiao

IPC: H01L21/28 ,  H01L29/423 ,  H01L27/11536 ,  H01L27/11539

CPC classification number: H01L21/28273 ,  H01L27/11536 ,  H01L27/11539 ,  H01L29/42336

Abstract: Provided is a memory device including a first gate, a second gate and an inter-gate dielectric layer. The first gate is buried in a substrate. The second gate includes metal and is disposed on the substrate. The inter-gate dielectric layer is disposed between the first and second gates. A method of forming a memory device is further provided.

公开(公告)号：US20160336417A1

公开(公告)日：2016-11-17

申请号：US14749610

申请日：2015-06-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Kun-Huang Yu ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chih-Chung Wang

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/51 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/06

CPC classification number: H01L29/42368 ,  H01L21/28167 ,  H01L21/3085 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66613 ,  H01L29/66621 ,  H01L29/78

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; using a first patterned mask to form a gate dielectric layer on the substrate; removing the first patterned mask; removing part of the gate dielectric layer; and forming a shallow trench isolation (STI) adjacent to two sides of the gate dielectric layer.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供衬底; 使用第一图案化掩模在衬底上形成栅极电介质层; 去除第一图案化掩模; 去除所述栅介电层的一部分; 以及在所述栅极介电层的两侧形成浅沟槽隔离（STI）。

公开(公告)号：US20160336410A1

公开(公告)日：2016-11-17

申请号：US14739702

申请日：2015-06-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Kai-Kuen Chang ,  Kun-Huang Yu

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L29/404 ,  H01L21/762 ,  H01L23/485 ,  H01L23/522 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a source region, a drain region, a gate, and a dummy contact. The source region and the drain region are formed in the substrate. The gate is formed on the substrate and between the source region and the drain region. The dummy contact includes a plurality of dummy plugs formed on the substrate, wherein the dummy plugs have depths decreasing towards the drain region.

Abstract translation: 提供半导体结构及其制造方法。 半导体结构包括衬底，源极区，漏极区，栅极和虚拟接触。 源极区域和漏极区域形成在衬底中。 栅极形成在衬底上并且在源极区域和漏极区域之间。 虚拟触点包括形成在基板上的多个虚拟插头，其中虚拟插头具有朝向漏极区域减小的深度。

公开(公告)号：US20160233313A1

公开(公告)日：2016-08-11

申请号：US15132256

申请日：2016-04-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Huang Yu ,  Shih-Yin Hsiao

IPC: H01L29/66 ,  H01L29/40

CPC classification number: H01L29/66545 ,  H01L21/76895 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/401 ,  H01L29/402 ,  H01L29/4238 ,  H01L29/66568 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7835

Abstract: A method for manufacturing a MOS transistor device includes following steps. A substrate including at least an isolation structure formed therein is provided. Next, a MOS transistor device is formed on the substrate, the MOS transistor device includes a gate, a source region, a drain region and a spacer. After forming the MOS transistor device, at least a first dummy contact is formed on a drain side of the gate and a gate contact is formed to be electrically connected to the gate. The first dummy contact is spaced apart from a surface of the substrate and electrically connected to the gate contact.

Abstract translation: 一种用于制造MOS晶体管器件的方法包括以下步骤。 提供了至少包括形成在其中的隔离结构的基板。 接下来，在基板上形成MOS晶体管器件，MOS晶体管器件包括栅极，源极区域，漏极区域和间隔物。 在形成MOS晶体管器件之后，在栅极的漏极侧形成至少第一虚拟触点，并且形成与栅极电连接的栅极接触。 第一虚拟触点与衬底的表面间隔开并且电连接到栅极触点。

公开(公告)号：US20140339632A1

公开(公告)日：2014-11-20

申请号：US13893635

申请日：2013-05-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Huang Yu

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/404 ,  H01L29/0649 ,  H01L29/407 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/7816

Abstract: A semiconductor structure comprises a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate and extending down from a surface of the substrate; a first well and a second well respectively having the first and second conductive types formed in the deep well, and extending down from the surface of the substrate; a gate electrode formed on the substrate and disposed between the first and second wells; an isolation extending down from the surface of the substrate and disposed between the gate electrode and the second well; a conductive plug including a first portion and a second portion electrically connected to each other, and the first portion electrically connected to the gate electrode, and the second portion comprising at least two fingers penetrating into the isolation, and the fingers spaced apart and electrically connected to each other.

Abstract translation: 半导体结构包括具有第一导电类型的衬底; 具有形成在所述基板中并从所述基板的表面向下延伸的第二导电类型的深阱; 第一阱和第二阱分别具有形成在深阱中的第一和第二导电类型，并从衬底的表面向下延伸; 栅电极，形成在所述基板上并且设置在所述第一阱和所述第二阱之间; 从衬底的表面向下延伸并且设置在栅电极和第二阱之间的隔离件; 导电插头，包括彼此电连接的第一部分和第二部分，并且所述第一部分电连接到所述栅电极，并且所述第二部分包括穿透到所述隔离物中的至少两个手指，并且所述手指间隔开并电连接 对彼此。

公开(公告)号：US20140225192A1

公开(公告)日：2014-08-14

申请号：US14253365

申请日：2014-04-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chiu-Te Lee ,  Ke-Feng Lin ,  Shu-Wen Lin ,  Kun-Huang Yu ,  Chih-Chung Wang ,  Te-Yuan Wu

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/407

Abstract: A semiconductor structure comprises a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate; a first well having the first conductive type and a second well having the second conductive type both formed in the deep well and the second well spaced apart from the first well; a gate electrode formed on the substrate and disposed between the first and second wells; an isolation extending down from the surface of the substrate and disposed between the gate electrode and the second well; a conductive plug including a first portion and a second portion electrically connected to each other, and the first portion electrically connected to the gate electrode, and the second portion penetrating into the isolation. The bottom surface of the second portion of the conductive plug is covered by the isolation.

Abstract translation: 半导体结构包括具有第一导电类型的衬底; 在衬底中形成有第二导电类型的深阱; 具有第一导电类型的第一阱和具有第二导电类型的第二阱都形成在深阱中并且第二阱与第一阱间隔开; 栅电极，形成在所述基板上并且设置在所述第一阱和所述第二阱之间; 从衬底的表面向下延伸并且设置在栅电极和第二阱之间的隔离件; 导电插头，其包括彼此电连接的第一部分和第二部分，并且所述第一部分电连接到所述栅电极，并且所述第二部分穿透所述隔离。 导电插头的第二部分的底表面被隔离层覆盖。

公开(公告)号：US20180005835A1

公开(公告)日：2018-01-04

申请号：US15705014

申请日：2017-09-14

Applicant: United Microelectronics Corp.

Inventor： Kun-Huang Yu ,  Shih-Yin Hsiao

IPC: H01L21/28 ,  H01L27/11536 ,  H01L27/11539 ,  H01L29/423

CPC classification number: H01L29/40114 ,  H01L27/11536 ,  H01L27/11539 ,  H01L29/42336

Abstract: Provided is a memory device including a first gate, a second gate and an inter-gate dielectric layer. The first gate is buried in a substrate. The second gate includes metal and is disposed on the substrate. The inter-gate dielectric layer is disposed between the first and second gates. The inter-gate dielectric layer comprises a high-k layer having a dielectric constant of greater than about 10.