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公开(公告)号：US20160003888A1
公开(公告)日：2016-01-07
申请号：US14321841
申请日：2014-07-02
Applicant: United Microelectronics Corp.
Inventor： Wen-Yin Weng , Wei-Heng Hsu , Cheng-Tung Huang , Yi-Ting Wu , Yu-Ming Lin , Jen-Yu Wang
IPC: G01R31/26
CPC classification number: G01R31/2621
Abstract: A method of characterizing a device may be used to determine a metal work function of the device according to a threshold voltage, a body effect, and an oxide capacitance of the device. The threshold voltage may be determined according to a current to voltage curve. The oxide capacitance may be determined according to a capacitor to voltage curve.
Abstract translation: 可以使用表征器件的方法来根据器件的阈值电压，体效应和氧化物电容来确定器件的金属功函数。 可以根据电流 - 电压曲线来确定阈值电压。 可以根据电容器对电压曲线来确定氧化物电容。
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公开(公告)号：US20250072007A1
公开(公告)日：2025-02-27
申请号：US18946884
申请日：2024-11-13
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Yi-Ting Wu , Cheng-Tung Huang , Jen-Yu Wang , Yung-Ching Hsieh , Po-Chun Yang , Jian-Jhong Chen , Bo-Chang Li
Abstract: A MRAM layout structure with multiple unit cells, including a first word line, a second word line and a third word line extending through active areas, wherein two ends of a first MTJ are connected respectively to a second active area and one end of a second MTJ, and two ends of a third MTJ are connected respectively to a third active area and one end of a fourth MTJ, and a first bit line and a second bit line connected respectively to the other end of the second MTJ and the other end of the fourth MTJ.
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公开(公告)号：US11955154B2
公开(公告)日：2024-04-09
申请号：US17744746
申请日：2022-05-16
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Cheng-Tung Huang , Jen-Yu Wang , Po-Chun Yang , Yi-Ting Wu , Yung-Ching Hsieh , Jian-Jhong Chen , Chia-Wei Lee
CPC classification number: G11C11/1673
Abstract: A sense amplifier circuit includes a sense amplifier, a switch and a temperature compensation circuit. The temperature compensation circuit provides a control signal having a positive temperature coefficient, based on which the switch provides reference impedance for temperature compensation. The sense amplifier includes a first input end coupled to a target bit and a second input end coupled to the switch. The sense amplifier outputs a sense amplifier signal based on the reference impedance and the impedance of the target bit.
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公开(公告)号：US20140343880A1
公开(公告)日：2014-11-20
申请号：US13894021
申请日：2013-05-14
Applicant: United Microelectronics Corp.
Inventor： Yi-Ting Wu , Cheng-Tung Huang , Tsung-Han Lee , Yi-Han Ye
CPC classification number: G01R19/0084 , G01R31/2621
Abstract: A method for deriving characteristic values of a MOS transistor is described. A set of ηk values is provided. A set of VBi values (i=1 to M, M≧3) is provided. A set of RSDi,j (i=1 to M−1, j=i+1 to M) values each under a pair of VBi and VBj, or a set of Vtq—q,j (q is one of 1 to M, j is 1 to M excluding q) values under VBq is derived for each ηk, with an iteration method. The ηk value making the set of RSDi,j values or Vtq—q,j values closest to each other is determined as an accurate ηk value. The mean value of RSDi,j at the accurate ηk value is calculated as an accurate RSD value.
Abstract translation: 描述用于导出MOS晶体管的特性值的方法。 提供了一组＆eegr k值。 提供一组VBi值（i = 1〜M，M≥3）。 一组RSDi，j（i = 1〜M-1，j = i + 1〜M）的值分别为一对VBi和VBj，或一组Vtq-q，j（q为1〜M ，j为1到M，不包括q）使用迭代方法为每个＆eegr k导出VBq下的值。 使得最接近的RSDi，j值或Vtq-q，j值的集合被确定为精确的k值。 RSDi，j在精确的k值的平均值被计算为准确的RSD值。
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公开(公告)号：US12190926B2
公开(公告)日：2025-01-07
申请号：US18108025
申请日：2023-02-10
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hung-Chan Lin , Jia-Rong Wu , Yi-Ting Wu
Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region, a second cell region, a third cell region, and a fourth cell region, a first gate pattern extending from the first cell region to the third cell region along a first direction, a first diffusion region extending from the first cell region to the second cell region along a second direction, a first metal pattern adjacent to one side of the first gate pattern and overlapping the first diffusion region, a source line pattern extending from the first cell region to the second cell region along the second direction, and a first spin orbit torque (SOT) pattern extending along the first direction and overlapping the first metal pattern and the source line pattern.
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Patent Agency Ranking
公开(公告)号：US12178052B2
公开(公告)日：2024-12-24
申请号：US17368848
申请日：2021-07-07
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Yi-Ting Wu , Cheng-Tung Huang , Jen-Yu Wang , Yung-Ching Hsieh , Po-Chun Yang , Jian-Jhong Chen , Bo-Chang Li
Abstract: A MRAM circuit structure is provided in the present invention, with the unit cell composed of three transistors in series and four MTJs, wherein the junction between first transistor and third transistor is first node, the junction between second transistor and third transistor is second node, and the other ends of first transistor and third transistor are connected to a common source line. First MTJ is connected to second MTJ in series to form a first MTJ pair that connecting to the first node, and third MTJ is connected to fourth MTJ in series to form a second MTJ pair that connecting to the second node.
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17.发明授权公开(公告)号：US11942130B2
公开(公告)日：2024-03-26
申请号：US17701703
申请日：2022-03-23
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Jian-Jhong Chen , Yi-Ting Wu , Jen-Yu Wang , Cheng-Tung Huang , Po-Chun Yang , Yung-Ching Hsieh
CPC classification number: G11C11/161 , H10B61/00 , H10N50/01 , H10N50/10 , H10N50/80 , H10N50/85 , G11C11/15 , G11C11/165
Abstract: A bottom-pinned spin-orbit torque magnetic random access memory (SOT-MRAM) is provided in the present invention, including a substrate, a bottom electrode layer on the substrate, a magnetic tunnel junction (MTJ) on the bottom electrode layer, a spin-orbit torque (SOT) layer on the MTJ, a capping layer on the SOT layer, and an injection layer on the capping layer, wherein the injection layer is divided into individual first part and second part, and the first part and the second part are connected respectively with two ends of the capping layer.
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公开(公告)号：US20230018513A1
公开(公告)日：2023-01-19
申请号：US17952327
申请日：2022-09-26
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chun-Yen Tseng , Shu-Ru Wang , Yu-Tse Kuo , Chang-Hung Chen , Yi-Ting Wu , Shu-Wei Yeh , Ya-Lan Chiou , Chun-Hsien Huang
Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region and a second cell region and a diffusion region on the substrate extending through the first cell region and the second cell region. Preferably, the diffusion region includes a first H-shape and a second H-shape according to a top view.
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公开(公告)号：US11355695B2
公开(公告)日：2022-06-07
申请号：US16852542
申请日：2020-04-19
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Yi-Ting Wu , Yan-Jou Chen , Cheng-Tung Huang , Jen-Yu Wang , Po-Chun Yang , Yung-Ching Hsieh , Jian-Jhong Chen , Bo-Chang Li
Abstract: A memory device includes a substrate; an active area extending along a first direction on the substrate; a gate line traversing the active area and extending along a second direction that is not parallel to the first direction; a source doped region in the active area and on a first side of the gate line; a main source line extending along the first direction; a source line extension coupled to the main source line and extending along the second direction; a drain doped region in the active area and on a second side of the gate line that is opposite to the first side; and a data storage element electrically coupled to the drain doped region. The main source line is electrically connected to the source doped region via the source line extension.
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公开(公告)号：US11238912B1
公开(公告)日：2022-02-01
申请号：US17146424
申请日：2021-01-11
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Yi-Ting Wu , Cheng-Tung Huang , Jen-Yu Wang , Yung-Ching Hsieh , Po-Chun Yang , Jian-Jhong Chen , Bo-Chang Li
Abstract: In an MRAM, each unit cell includes two non-volatile storage units, three N-type transistors and three P-type transistors. Each N-type transistor is coupled in parallel with a corresponding P-type transistor for forming a transmission gate which provides bi-directional current, thereby preventing source degeneration.
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