公开(公告)号：US10056463B2

公开(公告)日：2018-08-21

申请号：US15628592

申请日：2017-06-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Su Xing ,  Hsueh-Wen Wang ,  Chien-Yu Ko ,  Yu-Cheng Tung ,  Jen-Yu Wang ,  Cheng-Tung Huang ,  Yu-Ming Lin

IPC: H01L21/28 ,  H01L29/51 ,  H01L29/786 ,  H01L29/66 ,  H01L27/11585

CPC classification number: H01L29/516 ,  H01L27/11585 ,  H01L29/40111 ,  H01L29/42376 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/6684 ,  H01L29/66969 ,  H01L29/7869

Abstract: A transistor includes a semiconductor channel layer, a gate structure, a gate insulation layer, an internal electrode, and a ferroelectric material layer. The gate structure is disposed on the semiconductor channel layer. The gate insulation layer is disposed between the gate structure and the semiconductor channel layer. The internal electrode is disposed between the gate insulation layer and the gate structure. The ferroelectric material layer is disposed between the internal electrode and the gate structure. A spacer is disposed on the semiconductor channel layer, and a trench surrounded by the spacer is formed above the semiconductor channel layer. The ferroelectric material layer is disposed in the trench, and the gate structure is at least partially disposed outside the trench. The ferroelectric material layer in the transistor of the present invention is used to enhance the electrical characteristics of the transistor.

公开(公告)号：US20180166444A1

公开(公告)日：2018-06-14

申请号：US15892366

申请日：2018-02-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Yin Weng ,  Cheng-Tung Huang ,  Wei-Heng Hsu ,  Yu-Ming Lin ,  Ya-Ru Yang

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/205 ,  H01L29/165 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8258 ,  H01L21/02

CPC classification number: H01L27/0886 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02639 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/8258 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/165 ,  H01L29/205 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/7851

Abstract: A fin shaped structure and a method of forming the same. The method includes providing a substrate having a first fin structure and a second fin structure. Next, an insulation material layer is formed on the substrate. Then, a portion of the first fin structure is removed, to form a first recess. Following this, a first buffer layer and a first channel layer are formed sequentially in the first recess. Next, a portion of the second fin structure is removed, to form a second recess. Then, a second buffer layer and a second channel layer are formed in the second recess sequentially, wherein the second buffer layer is different from the first buffer layer.

公开(公告)号：US20170040346A1

公开(公告)日：2017-02-09

申请号：US15296027

申请日：2016-10-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Yin Weng ,  Cheng-Tung Huang ,  Ya-Ru Yang ,  Yi-Ting Wu ,  Yu-Ming Lin ,  Jen-Yu Wang

IPC: H01L27/12 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/66 ,  H01L21/308 ,  H01L29/165 ,  H01L29/16 ,  H01L21/84 ,  H01L21/02

CPC classification number: H01L27/1207 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/02639 ,  H01L21/3081 ,  H01L21/76251 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for fabricating substrate of a semiconductor device includes the steps of: providing a first silicon layer; forming a dielectric layer on the first silicon layer; bonding a second silicon layer to the dielectric layer; removing part of the second silicon layer and part of the dielectric layer to define a first region and a second region on the first silicon layer, wherein the remaining of the second silicon layer and the dielectric layer are on the second region; and forming an epitaxial layer on the first region of the first silicon layer, wherein the epitaxial layer and the second silicon layer comprise same crystalline orientation.

Abstract translation: 一种制造半导体器件的衬底的方法包括以下步骤：提供第一硅层; 在所述第一硅层上形成介电层; 将第二硅层接合到介电层; 去除所述第二硅层的一部分和所述介电层的一部分以限定所述第一硅层上的第一区域和第二区域，其中所述第二硅层和所述介电层的剩余部分位于所述第二区域上; 以及在所述第一硅层的所述第一区上形成外延层，其中所述外延层和所述第二硅层包含相同的晶体取向。