公开(公告)号：US10734247B2

公开(公告)日：2020-08-04

申请号：US15803605

申请日：2017-11-03

Applicant: UTAC Headquarters PTE. LTD.

Inventor： Saravuth Sirinorakul ,  Suebphong Yenrudee

IPC: H01L21/48 ,  H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/498

Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a leadframe land grid array semiconductor package by using a laser to blast away un-designed conductive areas to create conductive paths on each molding compound layer of the semiconductor package.

公开(公告)号：US10600741B1

公开(公告)日：2020-03-24

申请号：US15832638

申请日：2017-12-05

Applicant: UTAC Headquarters PTE. LTD.

Inventor： Suebphong Yenrudee ,  Chanapat Kongpoung ,  Sant Hongsongkiat ,  Siriwanna Ounkaew ,  Chatchawan Injan ,  Saravuth Sirinorakul

IPC: H01L23/552 ,  H01L25/065 ,  H01L23/495 ,  H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L21/3205 ,  H01L21/3105 ,  H01L21/78 ,  H01L23/31

Abstract: Methods of manufacturing semiconductor packages with metal-plated shields include roughening surfaces of a molding compound by an abrasion process such that the surfaces have an unnatural surface roughness that is rougher than a natural surface roughness. In one embodiment, the method includes obtaining a molded array including a plurality of dies coupled to a substrate and a molding compound encapsulating the plurality of dies, coating all exposed surfaces of the molding compound with an adhesion promoter material, heating the molded array with an adhesion promoter material such that the adhesion promoter material reacts with a portion of the molding compound, resulting in a baked film, and etching away the baked film, resulting in the molding compound having the roughened surfaces. Preferably, the method also includes depositing a catalyst material on the roughened surfaces before a metal layer is coated on the roughened surfaces to speed up the time for the metal layer to adhere to the roughened surfaces.

公开(公告)号：US10361146B2

公开(公告)日：2019-07-23

申请号：US16243972

申请日：2019-01-09

Applicant: UTAC Headquarters PTE. LTD.

Inventor： Saravuth Sirinorakul ,  Keith M. Edwards ,  Suebphong Yenrudee ,  Albert Loh

IPC: H01L21/00 ,  H01L23/495 ,  H01L23/31 ,  H01L21/78 ,  H01L21/48

Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple leadframe routing layers in a plated and etched copper terminal semiconductor package by removing unwanted areas of each leadframe to create conductive paths on an associated leadframe layer of the semiconductor package.

公开(公告)号：US10325782B2

公开(公告)日：2019-06-18

申请号：US15673212

申请日：2017-08-09

Applicant: UTAC Headquarters PTE. LTD.

Inventor： Saravuth Sirinorakul ,  Suebphong Yenrudee

IPC: H01L21/48 ,  H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/498

Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using a laser to blast away un-designed conductive areas to create conductive paths on each molding compound layer of the semiconductor package.

公开(公告)号：US10032645B1

公开(公告)日：2018-07-24

申请号：US15347695

申请日：2016-11-09

Applicant: UTAC Headquarters PTE. LTD.

Inventor： Saravuth Sirinorakul ,  Suebphong Yenrudee

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/495 ,  H01L21/56

Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is fondled from multiple molding routing layers in a leadframe land grid array semiconductor package by using a laser to blast away un-designed conductive areas to create conductive paths on each molding compound layer of the semiconductor package.

公开(公告)号：US20170352610A1

公开(公告)日：2017-12-07

申请号：US15673212

申请日：2017-08-09

Applicant: UTAC Headquarters PTE. LTD.

Inventor： Saravuth Sirinorakul ,  Suebphong Yenrudee

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/78 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L21/4825 ,  H01L21/481 ,  H01L21/4828 ,  H01L21/4842 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4867 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49527 ,  H01L23/49534 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49558 ,  H01L23/49582 ,  H01L23/49586 ,  H01L23/49805 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45164 ,  H01L2224/45565 ,  H01L2224/45572 ,  H01L2224/48091 ,  H01L2224/48235 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2224/45664 ,  H01L2224/45644

Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using a laser to blast away un-designed conductive areas to create conductive paths on each molding compound layer of the semiconductor package.

公开(公告)号：US20170352555A1

公开(公告)日：2017-12-07

申请号：US15674449

申请日：2017-08-10

Applicant: UTAC Headquarters PTE. LTD.

Inventor： Saravuth Sirinorakul ,  Suebphong Yenrudee

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L23/495

CPC classification number: H01L21/4828 ,  H01L21/481 ,  H01L21/4825 ,  H01L21/4842 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4867 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49527 ,  H01L23/49534 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49558 ,  H01L23/49582 ,  H01L23/49586 ,  H01L23/49805 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45164 ,  H01L2224/45565 ,  H01L2224/45572 ,  H01L2224/48091 ,  H01L2224/48235 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2224/45664 ,  H01L2224/45644

Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using an inkjet process to create conductive paths on each molding compound layer of the semiconductor package.

公开(公告)号：US20170352554A1

公开(公告)日：2017-12-07

申请号：US15667433

申请日：2017-08-02

Applicant: UTAC Headquarters PTE. LTD.

Inventor： Saravuth Sirinorakul ,  Suebphong Yenrudee

IPC: H01L21/48 ,  H01L23/495

CPC classification number: H01L21/4825 ,  H01L21/481 ,  H01L21/4828 ,  H01L21/4842 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4867 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49527 ,  H01L23/49534 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49558 ,  H01L23/49582 ,  H01L23/49586 ,  H01L23/49805 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45164 ,  H01L2224/45565 ,  H01L2224/45572 ,  H01L2224/48091 ,  H01L2224/48235 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2224/45664 ,  H01L2224/45644

Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using a laser to activate areas of each molding compound layer of the semiconductor package. Each compound filler in the molding compound layer has a metal interior and an insulating outermost shell. The activated molding compound areas in the molding compound layer become metallized in an electroless plating solution to build conductive paths on the molding compound surface, while properties of non-activated molding compound areas are not changed.