公开(公告)号：US11417735B2

公开(公告)日：2022-08-16

申请号：US16831850

申请日：2020-03-27

Applicant: United Microelectronics Corp.

Inventor： Zhuona Ma ,  Mengkai Zhu ,  Runshun Wang ,  Hua-Kuo Lee

IPC: H01L21/28 ,  H01L21/311 ,  H01L21/3213

Abstract: A method for fabricating a semiconductor device is provided. The method includes providing a substrate, having a cell region and a logic region and including a first conductive layer as a top layer, wherein shallow trench isolation (STI) structures are disposed in the substrate at cell region and the logic region. A first dry etching process is performed to preliminarily etch the first conductive layer and the STI structures at the cell region. A wet etching process is performed over the substrate to etch the STI structures down to a preserved height. A control gate stack is formed on the first conductive layer at the cell region. A second dry etching process is performed on a portion of the first conductive layer to form a floating gate under the control gate stack at the cell region and remove the first conductive layer at the logic region.

公开(公告)号：US10319679B2

公开(公告)日：2019-06-11

申请号：US15849526

申请日：2017-12-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Mengkai Zhu

IPC: H01L21/768 ,  H01L29/66 ,  H01L23/528 ,  H01L21/762 ,  H01L21/033 ,  H01L29/06 ,  H01L29/78 ,  H01L21/74

Abstract: A semiconductor device includes: a substrate having a first semiconductor layer, an insulating layer, and a second semiconductor layer; an active device on the substrate; an interlayer dielectric (ILD) layer on the active device; a first contact plug adjacent to the active device; and a second contact plug in the ILD layer and electrically connected to the active device. Preferably, the first contact plug includes a first portion in the insulating layer and the second semiconductor layer and a second portion in the ILD layer, in which a width of the second portion is greater than a width of the first portion.

公开(公告)号：US20180331282A1

公开(公告)日：2018-11-15

申请号：US15594498

申请日：2017-05-12

Applicant: United Microelectronics Corp.

Inventor： Mengkai Zhu

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1233 ,  G11C13/0002 ,  G11C2213/52 ,  H01L27/2409 ,  H01L45/1253 ,  H01L45/16

Abstract: A resistive random access memory (RRAM) structure including a substrate, RRAM cells and protection layers is provided. The RRAM cells are adjacent to each other and disposed on the substrate. The protection layers are disposed respectively on sidewalls of the RRAM cells without covering top surfaces of the RRAM cells. Each of the protection layers includes a sidewall portion and an extension portion. The sidewall portion is disposed on each of the sidewalls of each of the RRAM cells. The extension portion is connected to a lower portion of the sidewall portion. An upper portion of the extension portion is lower than an upper portion of the sidewall portion. The extension portion is connected between the sidewall portions in a region between the RRAM cells.