公开(公告)号：US20210305377A1

公开(公告)日：2021-09-30

申请号：US16831850

申请日：2020-03-27

Applicant: United Microelectronics Corp.

Inventor： ZHUONA MA ,  Mengkai Zhu ,  Runshun Wang ,  Hua-Kuo Lee

IPC: H01L21/28 ,  H01L21/3213 ,  H01L21/311

Abstract: A method for fabricating a semiconductor device is provided. The method includes providing a substrate, having a cell region and a logic region and including a first conductive layer as a top layer, wherein shallow trench isolation (STI) structures are disposed in the substrate at cell region and the logic region. A first dry etching process is performed to preliminarily etch the first conductive layer and the STI structures at the cell region. A wet etching process is performed over the substrate to etch the STI structures down to a preserved height. A control gate stack is formed on the first conductive layer at the cell region. A second dry etching process is performed on a portion of the first conductive layer to form a floating gate under the control gate stack at the cell region and remove the first conductive layer at the logic region.

公开(公告)号：US20210020696A1

公开(公告)日：2021-01-21

申请号：US16538393

申请日：2019-08-12

Applicant: United Microelectronics Corp.

Inventor： Runshun Wang ,  Mengkai Zhu ,  Zhuona Ma ,  Hua-Kuo Lee

IPC: H01L27/24 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12 ,  H01L45/00

Abstract: The invention discloses a structure of a memory device. The structure includes a substrate, having a memory region and a logic region. A barrier layer is disposed on the substrate, covering the memory region and the logic region. A patterned inter-layer dielectric layer is disposed on the barrier layer only at the memory region. A first via structure is formed in the barrier layer and the patterned inter-layer dielectric layer at the memory region. A memory cell structure is disposed on the patterned inter-layer dielectric layer at the memory region, in contact with the first via structure. An interconnection structure is disposed on the barrier layer at the logic region.

公开(公告)号：US20150249158A1

公开(公告)日：2015-09-03

申请号：US14194957

申请日：2014-03-03

Applicant: United Microelectronics Corp.

Inventor： Wei Cheng ,  Hua-Kuo Lee ,  Ching-Long Tsai ,  Chi Ren ,  Cheng-Yuan Hsu

IPC: H01L29/788 ,  H01L21/3213 ,  H01L29/40

CPC classification number: H01L29/7883 ,  H01L27/11524 ,  H01L29/42328

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a substrate, a first gate structure, a second gate electrode, a third gate electrode and a protective layer. The first gate structure comprises a first gate electrode disposed on the substrate and a first gate dielectric covering the first gate electrode. The second gate electrode is disposed on and electrically isolated from the first gate electrode. The first gate structure has an extending portion relative to the second gate electrode. The third gate electrode is disposed adjacent to and electrically isolated from the first gate electrode and the second gate electrode. The third gate has an extending portion between a lower surface of the protective layer and an upper surface of the extending portion of the first gate structure.

Abstract translation: 提供半导体结构及其制造方法。 半导体结构包括衬底，第一栅极结构，第二栅电极，第三栅电极和保护层。 第一栅极结构包括设置在衬底上的第一栅极电极和覆盖第一栅电极的第一栅极电介质。 第二栅电极设置在第一栅电极上并与第一栅极电隔离。 第一栅极结构具有相对于第二栅电极的延伸部分。 第三栅电极设置成与第一栅电极和第二栅电极相邻并与之隔离。 第三栅极在保护层的下表面和第一栅极结构的延伸部分的上表面之间具有延伸部分。

公开(公告)号：US12142519B2

公开(公告)日：2024-11-12

申请号：US17748047

申请日：2022-05-19

Applicant: United Microelectronics Corp.

Inventor： Runshun Wang ,  Mengkai Zhu ,  Zhuona Ma ,  Hua-Kuo Lee

IPC: H01L21/768 ,  H01L21/66 ,  H01L23/522 ,  H01L23/532

Abstract: An etch stop detection structure and an etch stop detection method are provided. The etch stop detection structure includes a substrate, a first dielectric layer, a first stop layer, and a second dielectric layer. The substrate includes a device region and a detection region. The first dielectric layer is located on the substrate. The first stop layer is located on the first dielectric layer. The second dielectric layer is located on the first stop layer. There is a first air gap in the first dielectric layer and the first stop layer in the device region. There is a trench in the second dielectric layer in the detection region. The trench exposes the first stop layer. The etch stop detection structure can be used to detect the etch stop signal.

公开(公告)号：US20230343639A1

公开(公告)日：2023-10-26

申请号：US17748047

申请日：2022-05-19

Applicant: United Microelectronics Corp.

Inventor： Runshun Wang ,  Mengkai Zhu ,  Zhuona Ma ,  Hua-Kuo Lee

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/66

CPC classification number: H01L21/7682 ,  H01L21/76829 ,  H01L23/53295 ,  H01L22/30 ,  H01L22/26 ,  H01L23/5226

Abstract: An etch stop detection structure and an etch stop detection method are provided. The etch stop detection structure includes a substrate, a first dielectric layer, a first stop layer, and a second dielectric layer. The substrate includes a device region and a detection region. The first dielectric layer is located on the substrate. The first stop layer is located on the first dielectric layer. The second dielectric layer is located on the first stop layer. There is a first air gap in the first dielectric layer and the first stop layer in the device region. There is a trench in the second dielectric layer in the detection region. The trench exposes the first stop layer. The etch stop detection structure can be used to detect the etch stop signal.

公开(公告)号：US11417735B2

公开(公告)日：2022-08-16

申请号：US16831850

申请日：2020-03-27

Applicant: United Microelectronics Corp.

Inventor： Zhuona Ma ,  Mengkai Zhu ,  Runshun Wang ,  Hua-Kuo Lee

IPC: H01L21/28 ,  H01L21/311 ,  H01L21/3213

Abstract: A method for fabricating a semiconductor device is provided. The method includes providing a substrate, having a cell region and a logic region and including a first conductive layer as a top layer, wherein shallow trench isolation (STI) structures are disposed in the substrate at cell region and the logic region. A first dry etching process is performed to preliminarily etch the first conductive layer and the STI structures at the cell region. A wet etching process is performed over the substrate to etch the STI structures down to a preserved height. A control gate stack is formed on the first conductive layer at the cell region. A second dry etching process is performed on a portion of the first conductive layer to form a floating gate under the control gate stack at the cell region and remove the first conductive layer at the logic region.

公开(公告)号：US09786489B1

公开(公告)日：2017-10-10

申请号：US15461486

申请日：2017-03-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming Sheng Xu ,  Ching-Long Tsai ,  Hua-Kuo Lee ,  Guangjun Huang

IPC: H01L21/00 ,  H01L21/02 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L21/02063 ,  H01L21/76807 ,  H01L2224/45147 ,  H01L2924/01029 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10335

Abstract: A method of cleaning post-etch residues on a copper line includes providing a copper line which is divided into a first region and a second region. A dielectric layer is formed on the copper line. After that, the dielectric layer is etched to form openings in the dielectric layer. A number of openings within the first region is more than a number of openings in the second region. During the etching process, a potential difference is formed between the first region and the second region of the copper line. Finally, the dielectric layer and the copper line are cleaned by a solution with a PH value. The PH value has a special relation with the potential difference.