公开(公告)号：US10153432B2

公开(公告)日：2018-12-11

申请号：US15594498

申请日：2017-05-12

Applicant: United Microelectronics Corp.

Inventor： Mengkai Zhu

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

Abstract: A resistive random access memory (RRAM) structure including a substrate, RRAM cells and protection layers is provided. The RRAM cells are adjacent to each other and disposed on the substrate. The protection layers are disposed respectively on sidewalls of the RRAM cells without covering top surfaces of the RRAM cells. Each of the protection layers includes a sidewall portion and an extension portion. The sidewall portion is disposed on each of the sidewalls of each of the RRAM cells. The extension portion is connected to a lower portion of the sidewall portion. An upper portion of the extension portion is lower than an upper portion of the sidewall portion. The extension portion is connected between the sidewall portions in a region between the RRAM cells.

公开(公告)号：US20220367271A1

公开(公告)日：2022-11-17

申请号：US17874303

申请日：2022-07-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Mengkai Zhu

IPC: H01L21/768 ,  H01L21/762 ,  H01L29/786 ,  H01L27/12

Abstract: A semiconductor device includes: a substrate having a first semiconductor layer, an insulating layer, and a second semiconductor layer; an active device on the substrate; an interlayer dielectric (ILD) layer on the active device; a first contact plug in the ILD layer and electrically connected to the active device; and a second contact plug in the ILD layer and the insulating layer, wherein a top surface of the second contact plug is higher than a top surface of the ILD layer.

公开(公告)号：US20210305377A1

公开(公告)日：2021-09-30

申请号：US16831850

申请日：2020-03-27

Applicant: United Microelectronics Corp.

Inventor： ZHUONA MA ,  Mengkai Zhu ,  Runshun Wang ,  Hua-Kuo Lee

IPC: H01L21/28 ,  H01L21/3213 ,  H01L21/311

Abstract: A method for fabricating a semiconductor device is provided. The method includes providing a substrate, having a cell region and a logic region and including a first conductive layer as a top layer, wherein shallow trench isolation (STI) structures are disposed in the substrate at cell region and the logic region. A first dry etching process is performed to preliminarily etch the first conductive layer and the STI structures at the cell region. A wet etching process is performed over the substrate to etch the STI structures down to a preserved height. A control gate stack is formed on the first conductive layer at the cell region. A second dry etching process is performed on a portion of the first conductive layer to form a floating gate under the control gate stack at the cell region and remove the first conductive layer at the logic region.

公开(公告)号：US20180174966A1

公开(公告)日：2018-06-21

申请号：US15849526

申请日：2017-12-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Mengkai Zhu

IPC: H01L23/528 ,  H01L21/768 ,  H01L29/06 ,  H01L21/762 ,  H01L21/74 ,  H01L29/66 ,  H01L21/033 ,  H01L29/78

CPC classification number: H01L23/5283 ,  H01L21/0332 ,  H01L21/743 ,  H01L21/76224 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/485 ,  H01L29/0653 ,  H01L29/66492 ,  H01L29/7833

Abstract: A semiconductor device includes: a substrate having a first semiconductor layer, an insulating layer, and a second semiconductor layer; an active device on the substrate; an interlayer dielectric (ILD) layer on the active device; a first contact plug adjacent to the active device; and a second contact plug in the ILD layer and electrically connected to the active device. Preferably, the first contact plug includes a first portion in the insulating layer and the second semiconductor layer and a second portion in the ILD layer, in which a width of the second portion is greater than a width of the first portion.

公开(公告)号：US20210020696A1

公开(公告)日：2021-01-21

申请号：US16538393

申请日：2019-08-12

Applicant: United Microelectronics Corp.

Inventor： Runshun Wang ,  Mengkai Zhu ,  Zhuona Ma ,  Hua-Kuo Lee

IPC: H01L27/24 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12 ,  H01L45/00

Abstract: The invention discloses a structure of a memory device. The structure includes a substrate, having a memory region and a logic region. A barrier layer is disposed on the substrate, covering the memory region and the logic region. A patterned inter-layer dielectric layer is disposed on the barrier layer only at the memory region. A first via structure is formed in the barrier layer and the patterned inter-layer dielectric layer at the memory region. A memory cell structure is disposed on the patterned inter-layer dielectric layer at the memory region, in contact with the first via structure. An interconnection structure is disposed on the barrier layer at the logic region.

公开(公告)号：US20200328116A1

公开(公告)日：2020-10-15

申请号：US16403596

申请日：2019-05-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Mengkai Zhu

IPC: H01L21/768 ,  H01L21/762 ,  H01L27/12 ,  H01L29/786

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate, wherein the substrate comprises a first semiconductor layer, an insulating layer, and a second semiconductor layer; forming an active device on the substrate; forming an interlayer dielectric (ILD) layer on the substrate and the active device; forming a first contact plug in the ILD layer to electrically connect the active device; and forming a second contact plug in the ILD layer and the insulating layer after forming the first contact plug.

公开(公告)号：US09887159B1

公开(公告)日：2018-02-06

申请号：US15402249

申请日：2017-01-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Mengkai Zhu

IPC: H01L21/768 ,  H01L23/528 ,  H01L29/41 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L21/033 ,  H01L29/06 ,  H01L21/74

CPC classification number: H01L23/5283 ,  H01L21/0332 ,  H01L21/743 ,  H01L21/76224 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/485 ,  H01L29/0653 ,  H01L29/66492 ,  H01L29/7833

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first semiconductor layer, an insulating layer, and a second semiconductor layer; forming an active device on the substrate; forming an interlayer dielectric (ILD) layer on the substrate and the active device; forming a mask layer on the ILD layer; removing part of the mask layer, part of the ILD layer, and part of the insulating layer to form a first contact hole; forming a patterned mask on the mask layer and into the first contact hole; and removing part of the mask layer and part of the ILD layer to form a second contact hole exposing part of the active device.

公开(公告)号：US12142519B2

公开(公告)日：2024-11-12

申请号：US17748047

申请日：2022-05-19

Applicant: United Microelectronics Corp.

Inventor： Runshun Wang ,  Mengkai Zhu ,  Zhuona Ma ,  Hua-Kuo Lee

IPC: H01L21/768 ,  H01L21/66 ,  H01L23/522 ,  H01L23/532

Abstract: An etch stop detection structure and an etch stop detection method are provided. The etch stop detection structure includes a substrate, a first dielectric layer, a first stop layer, and a second dielectric layer. The substrate includes a device region and a detection region. The first dielectric layer is located on the substrate. The first stop layer is located on the first dielectric layer. The second dielectric layer is located on the first stop layer. There is a first air gap in the first dielectric layer and the first stop layer in the device region. There is a trench in the second dielectric layer in the detection region. The trench exposes the first stop layer. The etch stop detection structure can be used to detect the etch stop signal.

公开(公告)号：US20230343639A1

公开(公告)日：2023-10-26

申请号：US17748047

申请日：2022-05-19

Applicant: United Microelectronics Corp.

Inventor： Runshun Wang ,  Mengkai Zhu ,  Zhuona Ma ,  Hua-Kuo Lee

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/66

CPC classification number: H01L21/7682 ,  H01L21/76829 ,  H01L23/53295 ,  H01L22/30 ,  H01L22/26 ,  H01L23/5226

Abstract: An etch stop detection structure and an etch stop detection method are provided. The etch stop detection structure includes a substrate, a first dielectric layer, a first stop layer, and a second dielectric layer. The substrate includes a device region and a detection region. The first dielectric layer is located on the substrate. The first stop layer is located on the first dielectric layer. The second dielectric layer is located on the first stop layer. There is a first air gap in the first dielectric layer and the first stop layer in the device region. There is a trench in the second dielectric layer in the detection region. The trench exposes the first stop layer. The etch stop detection structure can be used to detect the etch stop signal.

公开(公告)号：US11437272B2

公开(公告)日：2022-09-06

申请号：US16403596

申请日：2019-05-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Mengkai Zhu

IPC: H01L21/768 ,  H01L21/762 ,  H01L29/786 ,  H01L27/12

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate, wherein the substrate comprises a first semiconductor layer, an insulating layer, and a second semiconductor layer; forming an active device on the substrate; forming an interlayer dielectric (ILD) layer on the substrate and the active device; forming a first contact plug in the ILD layer to electrically connect the active device; and forming a second contact plug in the ILD layer and the insulating layer after forming the first contact plug.