公开(公告)号：US10727234B2

公开(公告)日：2020-07-28

申请号：US15361479

申请日：2016-11-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Ding-Lung Chen ,  Xing Hua Zhang ,  Shan Liu ,  Runshun Wang ,  Chien-Fu Chen ,  Wei-Jen Wang ,  Chen-Hsien Hsu

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L27/11 ,  H01L27/092 ,  H01L29/06 ,  H01L27/02 ,  H01L21/8238

Abstract: The present invention provides a layout of a semiconductor transistor device including a first and a second active area, a first and a second gate, and a metal line. The first active and the second active area are extended along a first direction. The first gate and the second gate are extended along a second direction and crossed the first active area, to define two transistors. The two transistors are electrically connected with each other through a conductive layer. The metal line is disposed on the conductive layer and is electrically connected the two transistors respectively.

公开(公告)号：US12191195B2

公开(公告)日：2025-01-07

申请号：US17409756

申请日：2021-08-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Bo Tao ,  Runshun Wang ,  Li Wang ,  Ching-Yang Wen ,  Purakh Raj Verma ,  Dong Yin ,  Jian Xie

IPC: H01L21/768

Abstract: A method of fabricating an air gap includes receiving a first thickness information of an inter-metal dielectric layer formed on a substrate and receiving a second thickness information of an inter-layer dielectric layer formed on the substrate. Then, a first etching is performed, wherein the first etching includes etch the inter-metal dielectric layer based on a first etching control value corresponding to the first thickness information. After the first etching, a second etching is performed to etch the inter-layer dielectric layer based on a second etching control value corresponding to the second thickness information.

公开(公告)号：US20210305377A1

公开(公告)日：2021-09-30

申请号：US16831850

申请日：2020-03-27

Applicant: United Microelectronics Corp.

Inventor： ZHUONA MA ,  Mengkai Zhu ,  Runshun Wang ,  Hua-Kuo Lee

IPC: H01L21/28 ,  H01L21/3213 ,  H01L21/311

Abstract: A method for fabricating a semiconductor device is provided. The method includes providing a substrate, having a cell region and a logic region and including a first conductive layer as a top layer, wherein shallow trench isolation (STI) structures are disposed in the substrate at cell region and the logic region. A first dry etching process is performed to preliminarily etch the first conductive layer and the STI structures at the cell region. A wet etching process is performed over the substrate to etch the STI structures down to a preserved height. A control gate stack is formed on the first conductive layer at the cell region. A second dry etching process is performed on a portion of the first conductive layer to form a floating gate under the control gate stack at the cell region and remove the first conductive layer at the logic region.

公开(公告)号：US20210020696A1

公开(公告)日：2021-01-21

申请号：US16538393

申请日：2019-08-12

Applicant: United Microelectronics Corp.

Inventor： Runshun Wang ,  Mengkai Zhu ,  Zhuona Ma ,  Hua-Kuo Lee

IPC: H01L27/24 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12 ,  H01L45/00

Abstract: The invention discloses a structure of a memory device. The structure includes a substrate, having a memory region and a logic region. A barrier layer is disposed on the substrate, covering the memory region and the logic region. A patterned inter-layer dielectric layer is disposed on the barrier layer only at the memory region. A first via structure is formed in the barrier layer and the patterned inter-layer dielectric layer at the memory region. A memory cell structure is disposed on the patterned inter-layer dielectric layer at the memory region, in contact with the first via structure. An interconnection structure is disposed on the barrier layer at the logic region.

公开(公告)号：US12142519B2

公开(公告)日：2024-11-12

申请号：US17748047

申请日：2022-05-19

Applicant: United Microelectronics Corp.

Inventor： Runshun Wang ,  Mengkai Zhu ,  Zhuona Ma ,  Hua-Kuo Lee

IPC: H01L21/768 ,  H01L21/66 ,  H01L23/522 ,  H01L23/532

Abstract: An etch stop detection structure and an etch stop detection method are provided. The etch stop detection structure includes a substrate, a first dielectric layer, a first stop layer, and a second dielectric layer. The substrate includes a device region and a detection region. The first dielectric layer is located on the substrate. The first stop layer is located on the first dielectric layer. The second dielectric layer is located on the first stop layer. There is a first air gap in the first dielectric layer and the first stop layer in the device region. There is a trench in the second dielectric layer in the detection region. The trench exposes the first stop layer. The etch stop detection structure can be used to detect the etch stop signal.

公开(公告)号：US20230343639A1

公开(公告)日：2023-10-26

申请号：US17748047

申请日：2022-05-19

Applicant: United Microelectronics Corp.

Inventor： Runshun Wang ,  Mengkai Zhu ,  Zhuona Ma ,  Hua-Kuo Lee

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/66

CPC classification number: H01L21/7682 ,  H01L21/76829 ,  H01L23/53295 ,  H01L22/30 ,  H01L22/26 ,  H01L23/5226

Abstract: An etch stop detection structure and an etch stop detection method are provided. The etch stop detection structure includes a substrate, a first dielectric layer, a first stop layer, and a second dielectric layer. The substrate includes a device region and a detection region. The first dielectric layer is located on the substrate. The first stop layer is located on the first dielectric layer. The second dielectric layer is located on the first stop layer. There is a first air gap in the first dielectric layer and the first stop layer in the device region. There is a trench in the second dielectric layer in the detection region. The trench exposes the first stop layer. The etch stop detection structure can be used to detect the etch stop signal.

公开(公告)号：US11417735B2

公开(公告)日：2022-08-16

申请号：US16831850

申请日：2020-03-27

Applicant: United Microelectronics Corp.

Inventor： Zhuona Ma ,  Mengkai Zhu ,  Runshun Wang ,  Hua-Kuo Lee

IPC: H01L21/28 ,  H01L21/311 ,  H01L21/3213

Abstract: A method for fabricating a semiconductor device is provided. The method includes providing a substrate, having a cell region and a logic region and including a first conductive layer as a top layer, wherein shallow trench isolation (STI) structures are disposed in the substrate at cell region and the logic region. A first dry etching process is performed to preliminarily etch the first conductive layer and the STI structures at the cell region. A wet etching process is performed over the substrate to etch the STI structures down to a preserved height. A control gate stack is formed on the first conductive layer at the cell region. A second dry etching process is performed on a portion of the first conductive layer to form a floating gate under the control gate stack at the cell region and remove the first conductive layer at the logic region.