公开(公告)号：US20230329006A1

公开(公告)日：2023-10-12

申请号：US18207654

申请日：2023-06-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Jing-Yin Jhang ,  Yu-Ping Wang ,  Hung-Yueh Chen ,  Wei Chen

IPC: H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10B61/22 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first inter-metal dielectric (IMD) layer around the MTJ; forming a first metal interconnection adjacent to the MTJ; forming a stop layer on the first IMD layer; removing the stop layer to form an opening; and forming a channel layer in the opening to electrically connect the MTJ and the first metal interconnection.

公开(公告)号：US11716860B2

公开(公告)日：2023-08-01

申请号：US16882783

申请日：2020-05-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Jing-Yin Jhang ,  Yu-Ping Wang ,  Hung-Yueh Chen ,  Wei Chen

IPC: H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10B61/22 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first inter-metal dielectric (IMD) layer around the MTJ; forming a first metal interconnection adjacent to the MTJ; forming a stop layer on the first IMD layer; removing the stop layer to form an opening; and forming a channel layer in the opening to electrically connect the MTJ and the first metal interconnection.

公开(公告)号：US10756128B2

公开(公告)日：2020-08-25

申请号：US16244109

申请日：2019-01-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chih Lai ,  Shih-Min Chou ,  Ko-Wei Lin ,  Chin-Fu Lin ,  Wei-Chuan Tsai ,  Chun-Yao Yang ,  Chia-Fu Cheng ,  Yi-Syun Chou ,  Wei Chen

IPC: H01L27/14 ,  H01L27/146 ,  H01L21/768 ,  H01L49/02

Abstract: An integrated circuit device includes a complementary metal oxide semiconductor (CMOS) image sensor. The complementary metal oxide semiconductor (CMOS) image sensor includes a P-N junction photodiode, a transistor gate, a polysilicon plug and a stacked metal layer. The P-N junction photodiode is disposed in a substrate. The transistor gate and the polysilicon plug are disposed on the substrate, wherein the polysilicon plug is directly connected to the P-N junction photodiode. The stacked metal layer connects the polysilicon plug to the transistor gate, wherein the stacked metal layer includes a lower metal layer and an upper metal layer, and the lower metal layer includes a first metal silicide part contacting to the polysilicon plug. The present invention also provides a method of fabricating said integrated circuit device.

公开(公告)号：US20200212090A1

公开(公告)日：2020-07-02

申请号：US16244109

申请日：2019-01-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chih Lai ,  Shih-Min Chou ,  Ko-Wei Lin ,  Chin-Fu Lin ,  Wei-Chuan Tsai ,  Chun-Yao Yang ,  Chia-Fu Cheng ,  Yi-Syun Chou ,  Wei Chen

IPC: H01L27/146 ,  H01L49/02 ,  H01L21/768

Abstract: An integrated circuit device includes a complementary metal oxide semiconductor (CMOS) image sensor. The complementary metal oxide semiconductor (CMOS) image sensor includes a P-N junction photodiode, a transistor gate, a polysilicon plug and a stacked metal layer. The P-N junction photodiode is disposed in a substrate. The transistor gate and the polysilicon plug are disposed on the substrate, wherein the polysilicon plug is directly connected to the P-N junction photodiode. The stacked metal layer connects the polysilicon plug to the transistor gate, wherein the stacked metal layer includes a lower metal layer and an upper metal layer, and the lower metal layer includes a first metal silicide part contacting to the polysilicon plug. The present invention also provides a method of fabricating said integrated circuit device.

公开(公告)号：US20220336735A1

公开(公告)日：2022-10-20

申请号：US17857185

申请日：2022-07-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Wei Chen ,  Po-Kai Hsu ,  Yu-Ping Wang ,  Hung-Yueh Chen

IPC: H01L43/12 ,  H01F10/32 ,  H01L43/02

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection and a second metal interconnection in the first IMD layer; forming a channel layer on the first metal interconnection and the second metal interconnection; forming a magnetic tunneling junction (MTJ) stack on the channel layer; and removing the MTJ stack to form a MTJ.

公开(公告)号：US20220320420A1

公开(公告)日：2022-10-06

申请号：US17844741

申请日：2022-06-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chih Lai ,  Yi-Syun Chou ,  Ko-Wei Lin ,  Pei-Hsun Kao ,  Wei Chen ,  Chia-Fu Cheng ,  Chun-Yao Yang ,  Chia-Chang Hsu

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

Abstract: A magnetoresistive random access memory (MRAM) structure includes a magnetic tunnel junction (MTJ), and a top electrode which contacts an end of the MTJ. The top electrode includes a top electrode upper portion and a top electrode lower portion. The width of the top electrode upper portion is larger than the width of the top electrode lower portion. A bottom electrode contacts another end of the MTJ. The top electrode, the MTJ and the bottom electrode form an MRAM.

公开(公告)号：US11417838B2

公开(公告)日：2022-08-16

申请号：US16884060

申请日：2020-05-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Wei Chen ,  Po-Kai Hsu ,  Yu-Ping Wang ,  Hung-Yueh Chen

IPC: H01L43/12 ,  H01F10/32 ,  H01L43/02

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection and a second metal interconnection in the first IMD layer; forming a channel layer on the first metal interconnection and the second metal interconnection; forming a magnetic tunneling junction (MTJ) stack on the channel layer; and removing the MTJ stack to form a MTJ.

公开(公告)号：US20210343786A1

公开(公告)日：2021-11-04

申请号：US16882783

申请日：2020-05-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Jing-Yin Jhang ,  Yu-Ping Wang ,  Hung-Yueh Chen ,  Wei Chen

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/12 ,  H01L43/10

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first inter-metal dielectric (IMD) layer around the MTJ; forming a first metal interconnection adjacent to the MTJ; forming a stop layer on the first IMD layer; removing the stop layer to form an opening; and forming a channel layer in the opening to electrically connect the MTJ and the first metal interconnection.

公开(公告)号：US20210143212A1

公开(公告)日：2021-05-13

申请号：US17157952

申请日：2021-01-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei Chen ,  Hui-Lin Wang ,  Yu-Ru Yang ,  Chin-Fu Lin ,  Yi-Syun Chou ,  Chun-Yao Yang

IPC: H01L27/22 ,  H01L23/552 ,  H01L43/10 ,  H01F41/34 ,  H01L43/02 ,  G11C11/16 ,  H01F10/32 ,  H01L43/12

Abstract: A magnetic tunnel junction (MTJ) device includes two magnetic tunnel junction elements and a magnetic shielding layer. The two magnetic tunnel junction elements are arranged side by side. The magnetic shielding layer is disposed between the magnetic tunnel junction elements. A method of forming said magnetic tunnel junction (MTJ) device includes the following steps. An interlayer including a magnetic shielding layer is formed. The interlayer is etched to form recesses in the interlayer. The magnetic tunnel junction elements fill in the recesses. Or, a method of forming said magnetic tunnel junction (MTJ) device includes the following steps. A magnetic tunnel junction layer is formed. The magnetic tunnel junction layer is patterned to form magnetic tunnel junction elements. An interlayer including a magnetic shielding layer is formed between the magnetic tunnel junction elements.

公开(公告)号：US10290710B2

公开(公告)日：2019-05-14

申请号：US15696167

申请日：2017-09-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chih Lai ,  Ming-Chang Lu ,  Wei Chen ,  Hui-Lin Wang ,  Yi-Ting Liao ,  Chin-Fu Lin

IPC: H01L29/10 ,  H01L21/385 ,  H01L29/24 ,  H01L29/51 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a first gradient layer, two source/drain structures, a second gradient layer, and a gate. The first gradient layer is disposed on the substrate. The two source/drain structures are separately disposed on the first gradient layer. The second gradient layer is disposed on the two source/drain structures and the first gradient layer, and a second portion of the second gradient layer directly contacts a first portion of the first gradient layer. The gate is disposed on the second gradient layer, between the two source/drain structures.