公开(公告)号：US20230387280A1

公开(公告)日：2023-11-30

申请号：US17851048

申请日：2022-06-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yen-Tsai Yi ,  Wei-Chuan Tsai ,  Jin-Yan Chiou ,  Hsiang-Wen Ke

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/7783 ,  H01L29/2003 ,  H01L29/0847 ,  H01L29/66462

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a p-type semiconductor layer on the barrier layer, forming a titanium nitride (TiN) layer on the p-type semiconductor layer as a nitrogen to titanium (N/Ti) ratio of the TiN layer is greater than 1, forming a passivation layer on the TiN layer and the barrier layer, removing the passivation layer to form an opening, forming a gate electrode in the opening, and then forming a source electrode and a drain electrode adjacent to two sides of the gate electrode on the buffer layer.

公开(公告)号：US10134629B1

公开(公告)日：2018-11-20

申请号：US15696267

申请日：2017-09-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Yen-Tsai Yi ,  Wei-Chuan Tsai ,  En-Chiuan Liou ,  Chih-Wei Yang

IPC: H01L21/44 ,  H01L21/768 ,  H01L29/78 ,  H01L23/532 ,  H01L23/535

Abstract: A method for manufacturing a semiconductor structure includes the following steps. At first, a titanium layer is formed on a preformed layer. Then, a first titanium nitride layer is formed on the titanium layer. A first plasma treatment is applied to the first titanium nitride layer such that the first titanium nitride layer has a first N/Ti ratio. A second titanium nitride layer is formed on the first titanium nitride layer. A second plasma treatment is applied to the second titanium nitride layer such that the second titanium nitride layer has a second N/Ti ratio larger than the first N/Ti ratio.

公开(公告)号：US12183801B2

公开(公告)日：2024-12-31

申请号：US17510394

申请日：2021-10-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jin-Yan Chiou ,  Wei-Chuan Tsai ,  Yen-Tsai Yi ,  Hsiang-Wen Ke

IPC: H01L29/45 ,  H01L29/40

Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate structure on a substrate, forming a source/drain region adjacent to two sides of the gate structure, forming an epitaxial layer on the source/drain region, forming an interlayer dielectric (ILD) layer on the gate structure, forming a contact hole in the ILD layer to expose the epitaxial layer, forming a low stress metal layer in the contact hole, forming a barrier layer on the low stress metal layer, and forming an anneal process to form a first silicide layer and a second silicide layer.

公开(公告)号：US12089504B2

公开(公告)日：2024-09-10

申请号：US17361331

申请日：2021-06-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yen-Tsai Yi ,  Wei-Chuan Tsai ,  Jin-Yan Chiou ,  Hsiang-Wen Ke

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01

Abstract: A method for fabricating a magnetic random access memory (MRAM) device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, forming a first top electrode on the MTJ stack, and then forming a second top electrode on the first top electrode. Preferably, the first top electrode includes a gradient concentration while the second top electrode includes a non-gradient concentration.

公开(公告)号：US20240237550A1

公开(公告)日：2024-07-11

申请号：US18611753

申请日：2024-03-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jin-Yan Chiou ,  Wei-Chuan Tsai ,  Hsin-Fu Huang ,  Yen-Tsai Yi ,  Hsiang-Wen Ke

IPC: H10N50/80 ,  G11C11/16 ,  H01F10/32 ,  H01F41/32 ,  H10N50/01 ,  H10N50/85

CPC classification number: H10N50/80 ,  G11C11/161 ,  H10N50/01 ,  H01F10/3254 ,  H01F41/32 ,  H10N50/85

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a contact hole in the first IMD layer; forming a bottom electrode layer in the contact hole; forming a magnetic tunneling junction (MTJ) stack on the bottom electrode layer; and removing the MTJ stack and the bottom electrode layer to form a
MTJ on a bottom electrode. Preferably, the bottom electrode protrudes above a top surface of the first IMD layer.

公开(公告)号：US20220122915A1

公开(公告)日：2022-04-21

申请号：US17073413

申请日：2020-10-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yen-Tsai Yi ,  Wei-Chuan Tsai ,  Jin-Yan Chiou ,  Hsiang-Wen Ke

IPC: H01L23/535 ,  H01L23/522 ,  H01L23/532 ,  H01L21/321 ,  H01L21/768

Abstract: A semiconductor structure includes a substrate; a first inter-layer dielectric (ILD) layer on the substrate; an etch stop layer on the first ILD layer; a second inter-layer dielectric (ILD) layer on the etch stop layer; and a copper damascene interconnect layer disposed in the first ILD layer. A tungsten via structure is disposed in the second ILD layer and the etch stop layer, and is electrically connected to the copper damascene interconnect layer. The tungsten via structure includes a tungsten layer and a barrier layer surrounding the tungsten layer. An intermetallic layer is disposed between the barrier layer and the copper damascene interconnect layer.

公开(公告)号：US20190122925A1

公开(公告)日：2019-04-25

申请号：US16224818

申请日：2018-12-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Han Chen ,  Yen-Tsai Yi ,  Chun-Chieh Chiu ,  Min-Chuan Tsai ,  Wei-Chuan Tsai ,  Hsin-Fu Huang

IPC: H01L21/768 ,  H01L29/08 ,  H01L29/417 ,  H01L29/267 ,  H01L29/24 ,  H01L29/16 ,  H01L29/161 ,  H01L23/485 ,  H01L23/532 ,  H01L23/535 ,  H01L29/66

Abstract: A conductive structure includes a substrate including a first dielectric layer formed thereon, at least a first opening formed in the first dielectric layer, a low resistive layer formed in the opening, and a first metal bulk formed on the lower resistive layer in the opening. The first metal bulk directly contacts a surface of the first low resistive layer. The low resistive layer includes a carbonitride of a first metal material, and the first metal bulk includes the first metal material.

公开(公告)号：US20180151428A1

公开(公告)日：2018-05-31

申请号：US15361503

申请日：2016-11-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Han Chen ,  Yen-Tsai Yi ,  Chun-Chieh Chiu ,  Min-Chuan Tsai ,  Wei-Chuan Tsai ,  Hsin-Fu Huang

IPC: H01L21/768 ,  H01L23/535 ,  H01L23/532 ,  H01L29/08 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/78

CPC classification number: H01L21/76889 ,  H01L21/76805 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/53266 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/7848

Abstract: A conductive structure includes a substrate including a first dielectric layer formed thereon, at least a first opening formed in the first dielectric layer, a low resistive layer formed in the opening, and a first metal bulk formed on the lower resistive layer in the opening. The first metal bulk directly contacts a surface of the first low resistive layer. The low resistive layer includes a carbonitride of a first metal material, and the first metal bulk includes the first metal material.

公开(公告)号：US20250081568A1

公开(公告)日：2025-03-06

申请号：US18950155

申请日：2024-11-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jin-Yan Chiou ,  Wei-Chuan Tsai ,  Yen-Tsai Yi ,  Hsiang-Wen Ke

IPC: H01L29/45 ,  H01L29/40

Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate structure on a substrate, forming a source/drain region adjacent to two sides of the gate structure, forming an epitaxial layer on the source/drain region, forming an interlayer dielectric (ILD) layer on the gate structure, forming a contact hole in the ILD layer to expose the epitaxial layer, forming a low stress metal layer in the contact hole, forming a barrier layer on the low stress metal layer, and forming an anneal process to form a first silicide layer and a second silicide layer.

公开(公告)号：US20230094638A1

公开(公告)日：2023-03-30

申请号：US17510394

申请日：2021-10-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jin-Yan Chiou ,  Wei-Chuan Tsai ,  Yen-Tsai Yi ,  Hsiang-Wen Ke

IPC: H01L29/45 ,  H01L29/40

Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate structure on a substrate, forming a source/drain region adjacent to two sides of the gate structure, forming an epitaxial layer on the source/drain region, forming an interlayer dielectric (ILD) layer on the gate structure, forming a contact hole in the ILD layer to expose the epitaxial layer, forming a low stress metal layer in the contact hole, forming a barrier layer on the low stress metal layer, and forming an anneal process to form a first silicide layer and a second silicide layer.