公开(公告)号：US07065628B2

公开(公告)日：2006-06-20

申请号：US10158409

申请日：2002-05-29

Applicant: Juan-Carlos Calderon ,  Jing Ling ,  Jean-Michel Caia ,  Vivek Joshi ,  Anguo T. Huang

Inventor： Juan-Carlos Calderon ,  Jing Ling ,  Jean-Michel Caia ,  Vivek Joshi ,  Anguo T. Huang

IPC: G06F12/00

CPC classification number: H04L49/103 ,  H04L49/109 ,  H04L49/254

Abstract: Memory access efficiency for packet applications may be improved by transferring full partitions of data. The number of full partitions written to external memory may be increased by temporarily storing packets using on-chip memory that is on a chip with the processor. Before writing packets to external memory, packets of length smaller than the external memory partition size may be temporarily stored in the on-chip memory until an amount corresponding to a full or nearly full partition has been collected, at which point the data can be efficiently written to an external memory partition.

公开(公告)号：US06944728B2

公开(公告)日：2005-09-13

申请号：US10329283

申请日：2002-12-23

Applicant: Juan-Carlos Calderon ,  Jean-Michel Caia ,  Vivek Joshi ,  Jing Ling ,  Anguo T. Huang

Inventor： Juan-Carlos Calderon ,  Jean-Michel Caia ,  Vivek Joshi ,  Jing Ling ,  Anguo T. Huang

IPC: G06F12/00 ,  H04L12/56

CPC classification number: H04L49/103

Abstract: Interleaving memory access includes enabling data included in a receive flow of data to be stored in a first memory bank, enabling data included in a transmit flow of data to be stored in a second memory bank, and alternating access of data in the first memory bank with access of data in the second memory bank.

Abstract translation: 交错存储器访问包括允许包含在接收数据流中的数据被存储在第一存储体中，使包含在数据传输流中的数据能够存储在第二存储体中，以及交替访问第一存储体中的数据 具有访问第二存储体中的数据。

公开(公告)号：US06564328B1

公开(公告)日：2003-05-13

申请号：US09471795

申请日：1999-12-23

Applicant: Edward T. Grochowski ,  Vinod Sharma ,  Gregory S. Matthews ,  Vivek Joshi ,  Ralph M. Kling

Inventor： Edward T. Grochowski ,  Vinod Sharma ,  Gregory S. Matthews ,  Vivek Joshi ,  Ralph M. Kling

IPC: G06F126

CPC classification number: G06F9/3836 ,  G06F1/3203 ,  G06F1/329 ,  G06F9/3869 ,  Y02D10/24

Abstract: The present invention provides a digital-based mechanism for adjusting the power consumption in an integrated digital circuit such as a processor. The processor includes one or more functional units and a digital throttle that monitors activity states of the processor's functional units to estimate the processor's power consumption. One embodiment of the digital throttle includes one or more gate units, a monitor circuit, and a throttle circuit. Each gate unit controls the delivery of power delivery to a functional unit of the processor and provides a signal that indicates the activity state of its associated functional unit. The monitor circuit determines an estimated power consumption level from the signals and compares the estimated power consumption with a threshold power level. The throttle circuit adjusts the instruction flow in the processor if the estimated power consumption level exceeds the threshold power level.

Abstract translation: 本发明提供一种用于调整诸如处理器的集成数字电路中的功耗的基于数字的机构。 处理器包括一个或多个功能单元和数字油门，其监视处理器的功能单元的活动状态以估计处理器的功率消耗。 数字油门的一个实施例包括一个或多个门单元，监视器电路和节流电路。 每个门单元控制向处理器的功能单元的功率传递的传递，并且提供指示其相关功能单元的活动状态的信号。 监视电路根据信号确定估计的功率消耗电平，并将估计的功耗与阈值功率电平进行比较。 如果估计的功率消耗电平超过阈值功率电平，则节流电路调整处理器中的指令流。

公开(公告)号：US08136079B2

公开(公告)日：2012-03-13

申请号：US13187201

申请日：2011-07-20

Applicant: Kanak B. Agarwal ,  Vivek Joshi

Inventor： Kanak B. Agarwal ,  Vivek Joshi

IPC: G06F9/455 ,  G06F17/50 ,  G06F11/22

CPC classification number: G06F17/5036

Abstract: Disclosed is a computer implemented method and computer program product to determine metal oxide semiconductor (MOS) gate functional limitations. A simulator obtains a plurality of slices of a MOS gate, the slices each comprising at least one parameter, the parameter comprising a slice gate width and a slice gate length. The simulator determines a current for each slice based on a slice gate length of the slice to form a length-based current for each slice. The simulator determines a length-based current for the MOS gate by summing the length-based current for each slice. The simulator calculates a stress profile for each slice. The simulator determines a slice carrier mobility for each slice based on the stress profile of each slice. The simulator determines a carrier mobility-based current for each slice, based on each slice carrier mobility. The simulator determines a carrier mobility for the MOS gate based on the carrier mobility-based current for each slice. The simulator determines an effective length for the MOS gate based on the length-based current.

公开(公告)号：US20110281771A1

公开(公告)日：2011-11-17

申请号：US13079511

申请日：2011-04-04

Applicant: Elena Chernokalskaya ,  Vivek Joshi ,  Mark Kavonian ,  Dave Brewster

Inventor： Elena Chernokalskaya ,  Vivek Joshi ,  Mark Kavonian ,  Dave Brewster

IPC: C40B40/14 ,  C08G65/48

CPC classification number: B01D67/0088 ,  B01D67/0095 ,  B01D71/68 ,  Y10T428/249955 ,  Y10T428/249958 ,  Y10T428/31663 ,  Y10T428/31667

Abstract: The present invention provides synthetic membranes which are suitable as a human skin substitute for the investigation of transdermal diffusion of candidate pharmaceutical and cosmetic compounds. The membranes according to the present invention exhibit human skin-like permeability properties with respect to the diffusion of a wide range of compounds having widely different physico-chemical properties.

Abstract translation: 本发明提供合适的膜，其适合作为人皮肤替代物来研究候选药物和化妆品化合物的透皮扩散。 根据本发明的膜相对于具有广泛不同的物理化学性质的广泛范围的化合物的扩散，显示人皮肤透过性。

公开(公告)号：US07295564B2

公开(公告)日：2007-11-13

申请号：US10337615

申请日：2003-01-06

Applicant: Jing Ling ,  Juan-Carlos Calderon ,  Jean-Michel Caia ,  Anguo T. Huang ,  Vivek Joshi

Inventor： Jing Ling ,  Juan-Carlos Calderon ,  Jean-Michel Caia ,  Anguo T. Huang ,  Vivek Joshi

IPC: H04L12/54

CPC classification number: H04L49/3045 ,  H04L47/50 ,  H04L47/621 ,  H04L47/624 ,  H04L49/205 ,  H04L49/3027 ,  H04L49/3072 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9094

Abstract: A method and apparatus for providing a virtual output queue (VoQ) from a received set of data packets in a multi-service system. Each packet is divided into at least one partition, including a last partition that includes packet information, such as error status and packet length. The system receives the packet from a flow, parses the packet into partitions, including a first partition and the last partition, places each last partition into a linked list based on a time when the last partition was received, links the last partition to the first partition, and employs the linked list as the output queue. This system allows for rapid compilation and transmission of different sized packets, and obviates the need for the receiving processor to wait for the last partition to discard a bad packet.

Abstract translation: 一种用于在多业务系统中从接收的一组数据分组提供虚拟输出队列（VoQ）的方法和装置。 每个分组被分成至少一个分区，包括包括分组信息的最后一个分区，例如错误状态和分组长度。 系统从流接收数据包，将数据包解析为分区，包括第一个分区和最后一个分区，根据接收到最后一个分区的时间，将最后一个分区放入链表中，将最后一个分区链接到第一个分区 分区，并使用链表作为输出队列。 该系统允许不同大小的分组的快速编译和传输，并且避免了接收处理​​器等待最后一个分区丢弃坏分组的需要。

公开(公告)号：US07154853B2

公开(公告)日：2006-12-26

申请号：US10137753

申请日：2002-05-02

Applicant: Jean-Michel Caia ,  Jing Ling ,  Juan-Carlos Calderon ,  Vivek Joshi ,  Anguo T. Huang

Inventor： Jean-Michel Caia ,  Jing Ling ,  Juan-Carlos Calderon ,  Vivek Joshi ,  Anguo T. Huang

IPC: G01R31/08 ,  G06F11/00

CPC classification number: H04L12/5601 ,  H04L2012/5636 ,  H04L2012/5637

Abstract: A rate policing algorithm for packet flows is based on counters and threshold checking. The rate policing algorithm utilizes a state machine having four links: (1) compliant state to compliant state; (2) transition from compliant state to non-compliant state; (3) non-compliant state to non-compliant state; and (4) transition from non-compliant state to compliant state. Depending on the values obtained from the counters and utilizing the threshold values, it is determined whether a flow rate for packets is compliant or non-compliant.

公开(公告)号：US06892284B2

公开(公告)日：2005-05-10

申请号：US10242580

申请日：2002-09-11

Applicant: Jing Ling ,  Juan-Carlos Calderon ,  Jean-Michel Caia ,  Vivek Joshi ,  Anguo T. Huang ,  Steve J. Clohset

Inventor： Jing Ling ,  Juan-Carlos Calderon ,  Jean-Michel Caia ,  Vivek Joshi ,  Anguo T. Huang ,  Steve J. Clohset

IPC: G06F12/00 ,  G06F12/02 ,  H04L12/56

CPC classification number: H04L49/9047 ,  H04L49/90 ,  H04L49/901 ,  H04L2012/5681 ,  Y10S707/99953 ,  Y10S707/99956

Abstract: A memory is divided into a number of partitions. The partitions are grouped into a first group of partitions and a second group of partitions. When required by a port, a partition is assigned to the port from a pool of un-assigned partitions. The pool of un-assigned partitions comprises of un-assigned partitions from the first group of partitions and un-assigned partitions from the second group of partitions. The un-assigned partitions from the first group of partitions are assigned to the port until a first threshold is reached. The un-assigned partitions from the second group of partitions are assigned to the port after the first threshold is reached. A second threshold is used to limit a total number of partitions assigned to the port.

Abstract translation: 内存分为多个分区。 分区被分组成第一组分区和第二组分区。 当端口需要时，从未分配的分区池将分区分配给该端口。 未分配分区的池包括来自第一组分区的未分配分区和来自第二组分区的未分配分区。 来自第一组分区的未分配分区被分配给端口，直到达到第一阈值。 来自第二组分区的未分配分区在达到第一个阈值后分配给该端口。 第二个阈值用于限制分配给端口的分区的总数。

公开(公告)号：US06564331B1

公开(公告)日：2003-05-13

申请号：US09405825

申请日：1999-09-24

Applicant: Vivek Joshi

Inventor： Vivek Joshi

IPC: G06F132

CPC classification number: G06F9/30141 ,  G06F1/3228

Abstract: A mechanism is provided for reducing the power consumption of a register file by disabling unused register file read ports. A selected entry of the register file is hardwired to zero and the address of the selected entry is driven to the address decoder of the register file in response to a power-down condition. The power-down condition occurs when, for example, no valid address is driven to the read port, i.e. the read port is unused. For one embodiment of the invention, the selected entry is the zeroth entry of the register file, and the address lines are grounded when an address valid bit associated with the read port is not asserted.

Abstract translation: 提供了一种通过禁用未使用的寄存器文件读取端口来减少寄存器文件的功耗的机制。 寄存器文件的选定条目硬连线为零，并且所选条目的地址响应于掉电状态被驱动到寄存器堆的地址解码器。 当例如没有有效地址被驱动到读端口，即读端口未使用时，发生掉电状况。 对于本发明的一个实施例，所选择的条目是寄存器文件的第零条目，并且当与读取端口相关联的地址有效位未被确认时，地址线接地。

公开(公告)号：US5889693A

公开(公告)日：1999-03-30

申请号：US851220

申请日：1997-05-05

Applicant: Vivek Joshi ,  Sudarshan Kumar

Inventor： Vivek Joshi ,  Sudarshan Kumar

IPC: G06F7/50 ,  G06F7/505 ,  G06K7/50

CPC classification number: G06F7/5055 ,  G06F7/507

Abstract: A method and apparatus for a CMOS inverter is provided for incrementing a first number by a one, three, or multiple of two. The incrementing unit includes an extract/restore unit for extracting a number of least significant bits from the first number, thereby producing a second number. The number of least significant bits extracted is determined by the incrementing value. The incrementing unit further includes an adjusting unit for adding an adjusting value to the least significant bits extracted from the first number, thereby producing an adjusted least significant bits. The incrementing unit further includes an incrementor block for receiving the second number and incrementing the second number, thereby producing a fourth number. The the extract/restore unit further for restoring the adjusted least significant bits to the fourth number, thereby producing a final result.

Abstract translation: 提供了一种CMOS反相器的方法和装置，用于将第一数量增加一个，三个或两个倍数。 递增单元包括用于从第一数量提取多个最低有效位的提取/恢复单元，从而产生第二数量。 提取的最低有效位的数量由递增值确定。 增量单元还包括调整单元，用于将调整值与从第一数量提取的最低有效位相加，从而产生经调整的最低有效位。 递增单元还包括用于接收第二数量并递增第二数量的增量块，从而产生第四数。 所述提取/还原单元还用于将经调整的最低有效位恢复到第四数，从而产生最终结果。