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公开(公告)号：US20160276027A1
公开(公告)日：2016-09-22
申请号：US14977667
申请日：2015-12-22
Applicant: Winbond Electronics Corp.
Inventor： Lih-Wei Lin , I-Hsien Tseng , Ju-Chieh Cheng , Chia-Hung Lin , Tsung-Huan Tsai , Po-Wei Huang
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0064 , G11C13/0097 , G11C2013/0078 , G11C2013/0083 , G11C2213/79 , G11C2213/82
Abstract: A resistive memory and a data writing method for a resistive memory cell thereof are provided. The method includes: receiving and decoding a column address signal for generating a decoded result, and providing a word line voltage to a word line of the resistive memory cell; providing a constant current to one of a bit line and a source line of the resistive memory cell, and coupling a reference ground voltage to another one of the bit line and the source line of the resistive memory cell.
Abstract translation: 提供了一种用于其电阻式存储单元的电阻式存储器和数据写入方法。 该方法包括：接收和解码用于产生解码结果的列地址信号，并将字线电压提供给电阻存储器单元的字线; 向电阻存储单元的位线和源极线之一提供恒定电流，以及将参考接地电压耦合到电阻存储单元的位线和源极线中的另一个。
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公开(公告)号：US11289160B2
公开(公告)日：2022-03-29
申请号：US17067341
申请日：2020-10-09
Applicant: Winbond Electronics Corp.
Inventor： Lih-Wei Lin , Ju-Chieh Cheng , Lung-Chi Cheng , Ying-Shan Kuo , Yu-An Chen
Abstract: A data writing method is provided. According to the present application, the data writing method includes steps of receiving an expected data, performing a plurality of readings on a target storage unit to obtain a plurality of read data; determining whether the plurality of read data are the same as the expected data respectively to generate a plurality of comparison results; and performing a writing operation procedure on the target storage unit according to the plurality of comparison results and the expected data.
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公开(公告)号：US10818353B1
公开(公告)日：2020-10-27
申请号：US16684527
申请日：2019-11-14
Applicant: Winbond Electronics Corp.
Inventor： Tsung-Huan Tsai , Lih-Wei Lin , Wan-Ni Shih , Min-Yen Liu
Abstract: The present disclosure provides a method for ripening a resistive random access memory (RRAM). The method includes: obtaining a first RRAM, wherein the first RRAM includes a plurality of memory cells; performing a forming operation and an initial reset operation on the first RRAM to form a plurality of specific memory cells in the memory cells; reading a specific number of the specific cells, and determining a ripening cycle parameter according to the specific number; and performing a ripening operation on the first RRAM based on the ripening cycle parameter to ripen the first RRAM as a second RRAM.
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公开(公告)号：US10726890B2
公开(公告)日：2020-07-28
申请号：US16177460
申请日：2018-11-01
Applicant: Winbond Electronics Corp.
Inventor： Lih-Wei Lin , Yu-Cheng Chuang , Sung-Yi Lee
Abstract: A resistive memory apparatus including a memory cell array and a voltage selector circuit is provided. The memory cell array includes a plurality of memory cells. The voltage selector circuit is coupled to the memory cell array. The voltage selector circuit performs a voltage applying operation on the memory cells via a plurality of different signal transmission paths. Each of the signal transmission paths passes one of the memory cells. IR drops of two of the signal transmission paths are substantially identical, and signal transmission directions thereof are different. In addition, an operating method of a resistive memory apparatus is also provided.
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公开(公告)号：US20200027507A1
公开(公告)日：2020-01-23
申请号：US16103942
申请日：2018-08-15
Applicant: Winbond Electronics Corp.
Inventor： Lih-Wei Lin , Ju-Chieh Cheng , Tsung-Huan Tsai , I-Hsien Tseng
Abstract: An operating method of a resistive memory storage apparatus includes: applying a forming voltage to a memory cell and obtaining a cell current of the memory cell; and determining whether to adjust the forming voltage and apply the adjusted forming voltage to the memory cell according to a magnitude relationship between the cell current and a reference current. The memory cell to which the forming voltage is applied operates in a heavy forming mode and serves as a one-time programmable memory device.
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Patent Agency Ranking
公开(公告)号：US10439829B1
公开(公告)日：2019-10-08
申请号：US16264698
申请日：2019-02-01
Applicant: Winbond Electronics Corp.
Inventor： Lih-Wei Lin , Chi-Shun Lin , Seow Fong Lim
Abstract: A physical unclonable function code generating method includes: providing a plurality of non-volatile memory cell pairs including a first non-volatile memory cell and a second non-volatile memory cell; comparing an initial state of the first non-volatile memory cell with an initial state of the second non-volatile memory cell, and generating a first physical unclonable function code according to a comparison result of the state; calculating a formation ratio difference of a logical level in the first physical unclonable function code; and adjusting the formation ratio difference by interactively performing forming operations on the first non-volatile memory cell and the second non-volatile memory cell when the formation ratio difference is greater than or equal to a ratio threshold.
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公开(公告)号：US10347336B1
公开(公告)日：2019-07-09
申请号：US16040552
申请日：2018-07-20
Applicant: Winbond Electronics Corp.
Inventor： Tsung-Huan Tsai , Lih-Wei Lin , I-Hsien Tseng , Wen-Ting Wang
Abstract: The disclosure provides a method for obtaining optimal operating condition of a resistive random access memory (RRAM). The method includes: retrieving an RRAM chip and performing a forming operation and an initial reset operation thereto based on a first operating condition; segmenting the RRAM chip into blocks; performing a set operation to each of the blocks based on various operating voltages; obtaining a fail bit value of each of the blocks; generating an operating characteristic curve related to the RRAM chip based on the fail bit value of each of the blocks and the operating voltages, wherein the operating characteristic curve has a lowest fail bit value and an operating voltage window; and when the lowest fail bit value and the operating voltage window satisfy a first condition and a second condition, respectively, determining the first operating condition is an optimal operating condition of the RRAM chip.
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公开(公告)号：US20190088321A1
公开(公告)日：2019-03-21
申请号：US16118445
申请日：2018-08-31
Applicant: Winbond Electronics Corp.
Inventor： Lih-Wei Lin , Tsung-Huan Tsai , Chi-Shun Lin , Seow Fong Lim
IPC: G11C13/00
Abstract: An operating method of a resistive memory element includes: performing a thermal step on the resistive memory element; performing a set and reset cycle operation on the resistive memory element to increase a read margin of the resistive memory element after a thermal step; and determining whether the resistive memory element passes a read margin verification.
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公开(公告)号：US11776636B2
公开(公告)日：2023-10-03
申请号：US17571525
申请日：2022-01-09
Applicant: Winbond Electronics Corp.
Inventor： Lih-Wei Lin
CPC classification number: G11C16/26 , G11C16/0483 , G11C16/08 , G11C16/24
Abstract: A memory array and its operation method are provided. The array includes plural sets of word lines; plural bit lines; and plural memory cell each arranged at intersection of the plural sets of word lines and the plural bit lines. Each memory cell has first and second conductive filament component and a switch circuit, and one ends of the first and the second conductive filament components are coupled to corresponding bit lines and the other ends thereof are coupled to the switch circuit. In the differential mode, read is performed based on the reading currents of the first and the second conductive filament components. In the single-ended mode, read is performed based on a reference current and a reading current of the first or the second conductive filament component that is formed successfully.
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公开(公告)号：US20230223089A1
公开(公告)日：2023-07-13
申请号：US17571525
申请日：2022-01-09
Applicant: Winbond Electronics Corp.
Inventor： Lih-Wei Lin
CPC classification number: G11C16/26 , G11C16/0483 , G11C16/08 , G11C16/24
Abstract: A memory array and its operation method are provided. The array includes plural sets of word lines; plural bit lines; and plural memory cell each arranged at intersection of the plural sets of word lines and the plural bit lines. Each memory cell has first and second conductive filament component and a switch circuit, and one ends of the first and the second conductive filament components are coupled to corresponding bit lines and the other ends thereof are coupled to the switch circuit. In the differential mode, read is performed based on the reading currents of the first and the second conductive filament components. In the single-ended mode, read is performed based on a reference current and a reading current of the first or the second conductive filament component that is formed successfully.
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