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公开(公告)号：US20240087644A1
公开(公告)日：2024-03-14
申请号：US18457377
申请日：2023-08-29
Applicant: Winbond Electronics Corp.
Inventor： I-Hsien Tseng , Lung-Chi Cheng , Ju-Chieh Cheng , Jun-Yao Huang , Ping-Kun Wang
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C13/0007 , G11C2013/0083
Abstract: A forming operation of resistive memory device is provided. The operation includes: applying a pre-forming gate voltage and a pre-forming bit line voltage to a target memory cell; performing a dense switching forming operation, wherein the dense switching forming operation includes alternately performing dense set operations and dense reset operations on the target memory cell, wherein the dense set operation includes applying a dense switching gate voltage and a dense set bit line voltage; and performing a normal set operation on the target memory cell, wherein the normal set operation includes applying a normal set gate voltage and a normal set bit line voltage to the target memory cell, the normal set gate voltage is greater than the pre-forming gate voltage and the dense switching gate voltage, and the normal set bit line voltage is less than the pre-forming bit line voltage and the dense set bit line voltage.
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公开(公告)号：US11289160B2
公开(公告)日：2022-03-29
申请号：US17067341
申请日：2020-10-09
Applicant: Winbond Electronics Corp.
Inventor： Lih-Wei Lin , Ju-Chieh Cheng , Lung-Chi Cheng , Ying-Shan Kuo , Yu-An Chen
Abstract: A data writing method is provided. According to the present application, the data writing method includes steps of receiving an expected data, performing a plurality of readings on a target storage unit to obtain a plurality of read data; determining whether the plurality of read data are the same as the expected data respectively to generate a plurality of comparison results; and performing a writing operation procedure on the target storage unit according to the plurality of comparison results and the expected data.
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公开(公告)号：US20240347118A1
公开(公告)日：2024-10-17
申请号：US18319501
申请日：2023-05-18
Applicant: Winbond Electronics Corp.
Inventor： Lung-Chi Cheng , Shan-Hsuan Tsai , Ying-Shan Kuo , Ngatik Cheung , Ju-Chieh Cheng
CPC classification number: G11C16/3459 , G11C16/102
Abstract: A memory device and an enhance programming method thereof are provided. The enhance programming method includes: performing program and verifying operations on a plurality of memory cell groups of a memory division, where each of the memory cell group corresponds to at least one byte; calculating a programming time for completing program operation of each of the memory cell groups; setting an indication flag when the programming time is larger than a preset threshold value; and, when the indication flag is in a setting state, increasing at least one of a plurality of program operation parameters, and performing an enhancement programming operation on the memory cell groups of the memory division.
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公开(公告)号：US20210335421A1
公开(公告)日：2021-10-28
申请号：US17226052
申请日：2021-04-08
Applicant: Winbond Electronics Corp.
Inventor： Lih-Wei Lin , Lung-Chi Cheng , Ju-Chieh Cheng , Ying-Shan Kuo
IPC: G11C13/00
Abstract: A resistive memory storage apparatus including a memory cell, a selecting transistor and a memory controller is provided. The memory cell outputs a writing current during a writing pulse width period. The selecting transistor is coupled to the memory cell. The memory controller is coupled to the selecting transistor and the memory cell. The memory controller is configured to apply a control voltage that gradually changes to a predetermined voltage level to a control end of the selecting transistor during a resistance transition phase of the writing pulse width period and set the control voltage to the predetermined voltage level during a filament stabilization phase after the resistance transition phase, so as to limit the writing current to a predetermined current value. In addition, an operating method for a resistive memory storage apparatus is also provided.
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公开(公告)号：US12237017B2
公开(公告)日：2025-02-25
申请号：US18072723
申请日：2022-12-01
Applicant: Winbond Electronics Corp.
Inventor： Lung-Chi Cheng , Ying-Shan Kuo , Jun-Yao Huang , Ju-Chieh Cheng , Yu-Cheng Chuang
Abstract: A block erase method for a flash memory is provided. The block erase method is to perform block erase on a block with a predetermined block size. The block erase method includes: performing an erase verification on bytes byte-by-byte in the block when performing the block erase; checking an erase step of the byte when the byte does not pass the erase verification; when the erase step of the byte exceeds a predetermined threshold value, performing the block erase with a partitioned block smaller than the predetermined block size, and returning to an erase verification stage to perform the erase verification; and when the erase step of the bytes does not exceed the predetermined threshold value, continuing to perform the block erase with the predetermined block size, and returning to the erasure verification stage to continue to perform the erase verification.
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Patent Agency Ranking
公开(公告)号：US11437101B2
公开(公告)日：2022-09-06
申请号：US17226052
申请日：2021-04-08
Applicant: Winbond Electronics Corp.
Inventor： Lih-Wei Lin , Lung-Chi Cheng , Ju-Chieh Cheng , Ying-Shan Kuo
Abstract: A resistive memory storage apparatus including a memory cell, a selecting transistor and a memory controller is provided. The memory cell outputs a writing current during a writing pulse width period. The selecting transistor is coupled to the memory cell. The memory controller is coupled to the selecting transistor and the memory cell. The memory controller is configured to apply a control voltage that gradually changes to a predetermined voltage level to a control end of the selecting transistor during a resistance transition phase of the writing pulse width period and set the control voltage to the predetermined voltage level during a filament stabilization phase after the resistance transition phase, so as to limit the writing current to a predetermined current value. In addition, an operating method for a resistive memory storage apparatus is also provided.
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公开(公告)号：US20230274782A1
公开(公告)日：2023-08-31
申请号：US18072723
申请日：2022-12-01
Applicant: Winbond Electronics Corp.
Inventor： Lung-Chi Cheng , Ying-Shan Kuo , Jun-Yao Huang , Ju-Chieh Cheng , Yu-Cheng Chuang
CPC classification number: G11C16/16 , G11C16/3445 , G11C16/3431
Abstract: A block erase method for a flash memory is provided. The block erase method is to perform block erase on a block with a predetermined block size. The block erase method includes: performing an erase verification on bytes byte-by-byte in the block when performing the block erase; checking an erase step of the byte when the byte does not pass the erase verification; when the erase step of the byte exceeds a predetermined threshold value, performing the block erase with a partitioned block smaller than the predetermined block size, and returning to an erase verification stage to perform the erase verification; and when the erase step of the bytes does not exceed the predetermined threshold value, continuing to perform the block erase with the predetermined block size, and returning to the erasure verification stage to continue to perform the erase verification.
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公开(公告)号：US10978149B1
公开(公告)日：2021-04-13
申请号：US16872374
申请日：2020-05-12
Applicant: Winbond Electronics Corp.
Inventor： Ju-Chieh Cheng , Ying-Shan Kuo , Lih-Wei Lin , Lung-Chi Cheng
IPC: G11C13/00
Abstract: A resistive memory apparatus and an adjusting method for write-in voltage thereof are provided. The adjusting method for write-in voltage includes: selecting an under test memory cell array in a resistive memory; performing N reset operations on a plurality of memory cells of the under test memory cell array according to a reset voltage, and performing N set operations on the memory cells of the under test memory cell array according to a set voltage, wherein n is an integer greater than 1; calculating a reset time variation rate of the reset operations and a set time variation rate of the set operations; and adjusting a voltage value of one of the set voltage and the reset voltage according to the reset time variation rate and the set time variation rate.
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9.发明授权公开(公告)号：US10783962B2
公开(公告)日：2020-09-22
申请号：US16105991
申请日：2018-08-21
Applicant: Winbond Electronics Corp.
Inventor： Lih-Wei Lin , Lung-Chi Cheng , Min-Yen Liu , Huan-Ming Chiang
Abstract: A writing method of a resistive memory storage apparatus includes: applying one of a set voltage and a reset voltage serving as a first selected voltage to a memory cell and obtaining a first read current; applying a disturbance voltage to the memory cell and obtaining a second read current; and determining whether a relationship between the first and second read currents satisfies a preset relationship, and if not, applying the other of the set voltage and the reset voltage serving as a second selected voltage to the memory cell and applying the first selected voltage to the memory cell again. A polarity of the disturbance voltage is different from that of the first selected voltage, and the absolute value of the disturbance voltage is less than that of the second selected voltage. A resistive memory storage apparatus is also provided.
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公开(公告)号：US20190074059A1
公开(公告)日：2019-03-07
申请号：US16105991
申请日：2018-08-21
Applicant: Winbond Electronics Corp.
Inventor： Lih-Wei Lin , Lung-Chi Cheng , Min-Yen Liu , Huan-Ming Chiang
Abstract: A writing method of a resistive memory storage apparatus includes: applying one of a set voltage and a reset voltage serving as a first selected voltage to a memory cell and obtaining a first read current of the memory cell; applying a disturbance voltage to the memory cell and obtaining a second read current of the memory cell; and determining whether a relationship between the first and second read currents satisfies a preset relationship, and if not, applying the other of the set voltage and the reset voltage serving as a second selected voltage to the memory cell and applying the first selected voltage to the memory cell again. A polarity of the disturbance voltage is different from that of the second selected voltage, and the absolute value of the disturbance voltage is less than that of the second selected voltage. A resistive memory storage apparatus is also provided.
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