公开(公告)号：US06897680B2

公开(公告)日：2005-05-24

申请号：US10797484

申请日：2004-03-09

Applicant: James Schleicher ,  James Park ,  Sergey Shumarayev ,  Bruce Pedersen ,  Tony Ngai ,  Wei-Jen Huang ,  Victor Maruri ,  Rakesh Patel

Inventor： James Schleicher ,  James Park ,  Sergey Shumarayev ,  Bruce Pedersen ,  Tony Ngai ,  Wei-Jen Huang ,  Victor Maruri ,  Rakesh Patel

IPC: G06F7/50 ,  G06F7/506 ,  H03K19/173 ,  H03K19/177 ,  H03K19/0177

CPC classification number: G06F7/506 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/17792

Abstract: A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.

Abstract translation: 可编程逻辑器件具有许多可编程逻辑区域，以及可用于在几乎任何逻辑区域之间进行互连的相对通用的，可编程的互连资源。 此外，各种类型的更多本地互连资源与每个逻辑区域相关联，以便于在相邻或附近的逻辑区域之间建立互连，而不需要使用这些互连的通用互连资源。 本地互连资源通过相对直接的和因此的高速互连来支持逻辑区域的灵活聚集，优选地在逻辑区域的典型二维阵列中的水平和垂直方向。 由本地互连资源提供的逻辑区域聚类选项优选地在逻辑区域阵列内是无边界的或基本无边界的。

公开(公告)号：US06690195B1

公开(公告)日：2004-02-10

申请号：US10047810

申请日：2002-01-15

Applicant: Tony Ngai ,  Sergey Shumarayev ,  Wei-Jen Huang

Inventor： Tony Ngai ,  Sergey Shumarayev ,  Wei-Jen Huang

IPC: H03K19177

CPC classification number: G06F7/506 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1778

Abstract: Driver circuitry for programmable logic devices may include a module comprising a driver and associated hardware-programmable input and/or output routing connections. Instances of the generalized driver module may be included anywhere on the programmable logic device that driver circuitry having characteristics within the capabilities of the generalized module is needed. The circuitry of each instance of the module is hardware-customized to match the driver characteristics required for that instance. Driver circuits may be distributed throughout the interconnection conductor resources of the programmable logic device in such a way as to optimize re-buffering of signals propagating through those resources.

Abstract translation: 用于可编程逻辑器件的驱动器电路可以包括包括驱动器和相关联的硬件可编程输入和/或输出路由连接的模块。 广义驱动器模块的实例可以包括在可编程逻辑器件的任何地方，其中需要具有广义模块能力的特性的驱动器电路。 模块的每个实例的电路都是硬件自定义的，以匹配该实例所需的驱动程序特性。 驱动器电路可以分布在可编程逻辑器件的整个互连导体资源中，以便优化通过这些资源传播的信号的重新缓冲。

公开(公告)号：US06525564B2

公开(公告)日：2003-02-25

申请号：US10017199

申请日：2001-12-14

Applicant: James Schleicher ,  James Park ,  Sergey Shumarayev ,  Bruce Pedersen ,  Tony Ngai ,  Wei-Jen Huang ,  Victor Maruri ,  Rakesh Patel

Inventor： James Schleicher ,  James Park ,  Sergey Shumarayev ,  Bruce Pedersen ,  Tony Ngai ,  Wei-Jen Huang ,  Victor Maruri ,  Rakesh Patel

IPC: H03K190177

CPC classification number: G06F7/506 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/17792

Abstract: A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.

公开(公告)号：US08891513B1

公开(公告)日：2014-11-18

申请号：US13593247

申请日：2012-08-23

Applicant: Wei-Jen Huang ,  Chih-Tsung Huang ,  Jerry Vogler

Inventor： Wei-Jen Huang ,  Chih-Tsung Huang ,  Jerry Vogler

IPC: H04L12/56 ,  H04L12/715 ,  H04L12/707 ,  H04L12/937

CPC classification number: H04L45/64 ,  H04L45/22 ,  H04L49/253

Abstract: An example method is provided and includes generating a packet at a switch; and sending the packet from a designated source port to a plurality of egress ports over an overlay network that is to provide an alternate routing path having a lower latency characteristic compared to a standard routing path provided by a forwarding engine of the switch. In more particular embodiments, the overlay network includes one or more dedicated paths from the designated source port to the plurality of egress ports, and the one or more dedicated paths is determined from a mapping between the designated source port and the plurality of egress ports. In other instances, the mapping is provided in a routing table.

Abstract translation: 提供了一种示例性方法，并且包括在交换机处生成分组; 并且通过覆盖网络将分组从指定的源端口发送到多个出口端口，所述覆盖网络将提供与由交换机的转发引擎提供的标准路由路径相比具有较低等待时间特性的替代路由路径。 在更具体的实施例中，覆盖网络包括从指定的源端口到多个出口端口的一个或多个专用路径，并且从指定的源端口和多个出口端口之间的映射确定一个或多个专用路径。 在其他情况下，映射在路由表中提供。

公开(公告)号：US20100207669A1

公开(公告)日：2010-08-19

申请号：US12388544

申请日：2009-02-19

Applicant: Sheng-Chun Chueh ,  Wei-Jen Huang

Inventor： Sheng-Chun Chueh ,  Wei-Jen Huang

IPC: H03B19/00

CPC classification number: H03L7/08

Abstract: The invention relates to a frequency adjusting apparatus and the method therefor comprising an adjusting module, a comparing module, a processing module and an operating module. The adjusting module generates a frequency signal according to a predetermined signal after receiving a trigger signal and generates N adjusting signal according to N processing signal. The comparing module compares the N adjusting signal with the predetermined signal according to a predetermined manner and generates N comparing result. The processing module generates N processing signal according to the N comparing result. The operating module executes a specific operation with M adjusting signal of the N adjusting signal matching the predetermined rule and generates a operation signal, wherein the frequency of the operation signal is approximately equal to which of the predetermined signal. Wherein N and M are natural numbers and N≧M≧1, the adjusting module adjusts the operation frequency according to the operation signal.

Abstract translation: 本发明涉及一种频率调节装置及其方法，包括调整模块，比较模块，处理模块和操作模块。 调整模块在接收到触发信号之后根据预定信号产生频率信号，并根据N处理信号产生N个调整信号。 比较模块根据预定的方式将N调整信号与预定信号进行比较，并产生N个比较结果。 处理模块根据N个比较结果产生N个处理信号。 操作模块执行具有与预定规则匹配的N调整信号的M调整信号的特定操作，并产生操作信号，其中操作信号的频率近似等于预定信号中的哪一个。 其中N和M是自然数，N≥M≥1，调节模块根据操作信号调节操作频率。

公开(公告)号：US20100066674A1

公开(公告)日：2010-03-18

申请号：US12382507

申请日：2009-03-18

Applicant: Sheng-Chun Chueh ,  Wei-Jen Huang ,  Hung-Yi Lin

Inventor： Sheng-Chun Chueh ,  Wei-Jen Huang ,  Hung-Yi Lin

IPC: G09G5/08

CPC classification number: G06F3/03547 ,  G06F3/038

Abstract: The invention relates to a cursor controlling apparatus for controlling a cursor according to an input information comprising an input module, a processing module and a controlling module. The input module is used for generating the input information. The processing module coupled to the input module is used for generating processing data according to the input information. The controlling module is coupled to the processing module for comparing the processing data with a predetermined value to generate a comparing result and further generating a first control signal or a second control signal corresponding to the processing data and the compared result to control the cursor respectively.

Abstract translation: 本发明涉及一种用于根据包括输入模块，处理模块和控制模块的输入信息来控制光标的光标控制装置。 输入模块用于生成输入信息。 耦合到输入模块的处理模块用于根据输入信息产生处理数据。 控制模块耦合到处理模块，用于将处理数据与预定值进行比较以产生比较结果，并进一步产生对应于处理数据和比较结果的第一控制信号或第二控制信号以分别控制光标。

公开(公告)号：US20090001953A1

公开(公告)日：2009-01-01

申请号：US11819461

申请日：2007-06-27

Applicant: Wei-Jen Huang

Inventor： Wei-Jen Huang

IPC: G05F1/10 ,  G05F1/00

CPC classification number: G05F1/575

Abstract: The present invention discloses an LDO (Low DropOut) linear voltage regulator, which is based on an NMC (Nested Miller Compensation) architecture and can be capacitor-free, wherein an active resistor is added to the feedback path of the Miller compensation capacitor to increase the controllability of the damping factor, solve the problem of extensively using the output capacitor with a parasitic resistance, and solve the problem that a compromise must be made between the damping factor control and the system loop gain. Further, the present invention utilizes a capacitor-sharing technique to reduce the Miller capacitance required by the entire system and accelerate the stabilization of output voltage without influencing stability.

Abstract translation: 本发明公开了一种基于NMC（嵌套米勒补偿）架构的LDO（Low DropOut）线性稳压器，其可以是无电容的，其中有效电阻被添加到Miller补偿电容器的反馈路径中以增加 阻尼因子的可控性解决了使用具有寄生电阻的输出电容器的问题，并解决了阻尼因子控制和系统环路增益之间必须妥协的问题。 此外，本发明利用电容器共享技术来降低整个系统所需的米勒电容，并且加速输出电压的稳定性而不影响稳定性。

公开(公告)号：US06593772B2

公开(公告)日：2003-07-15

申请号：US10177785

申请日：2002-06-19

Applicant: Tony Ngai ,  Sergey Shumarayev ,  Wei-Jen Huang ,  Rakesh Patel ,  Tin Lai

Inventor： Tony Ngai ,  Sergey Shumarayev ,  Wei-Jen Huang ,  Rakesh Patel ,  Tin Lai

IPC: H03K19177

CPC classification number: G11C5/025 ,  H03K19/17736 ,  H03K19/1776

Abstract: A high-performance programmable logic architecture has embedded memory (608). arranged at the peripheries or edges of the integrated circuit. This enhances the performance of the programmable logic integrated circuit by shortening the lengths of the programmable interconnect (748). In a specific embodiment, the memory blocks (703) are organized in rows along the top and bottom edges of the integrated circuit. The logic elements (805) can be directly programmable routed and connected to driver blocks (809) of the logic block in adjacent rows and columns. This permits fast interconnection of signals without using the global programmable interconnect resources (815, 825). Using similar direct programmable interconnections (828, 830, 835), the logic blocks can directly programmable connect to the memory blocks without using the global programmable interconnect resources. The present invention also provides technique of flexibly combining or stitching multiple memories together to form memories of a desired size.

公开(公告)号：US06407576B1

公开(公告)日：2002-06-18

申请号：US09516921

申请日：2000-03-02

Applicant: Tony Ngai ,  Bruce Pedersen ,  Sergey Shumarayev ,  James Schleicher ,  Wei-Jen Huang ,  Michael Hutton ,  Victor Maruri ,  Rakesh Patel ,  Peter J. Kazarian ,  Andrew Leaver ,  David W. Mendel ,  Jim Park

Inventor： Tony Ngai ,  Bruce Pedersen ,  Sergey Shumarayev ,  James Schleicher ,  Wei-Jen Huang ,  Michael Hutton ,  Victor Maruri ,  Rakesh Patel ,  Peter J. Kazarian ,  Andrew Leaver ,  David W. Mendel ,  Jim Park

IPC: H01L2500

CPC classification number: G06F7/506 ,  H03K19/1737 ,  H03K19/177 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/17792

Abstract: A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.

Abstract translation: 可编程逻辑集成电路器件具有多个可编程逻辑区域，该多个可编程逻辑区域设置在该区域的多个相交行和列中的该器件上。 在设备上提供互连资源（例如，互连导体，信号缓冲器/驱动器，可编程连接器等），用于对区域之间，从区域和/或区域之间进行可编程互连。 这些互连资源中的至少一些以架构上相似的两种形式提供（例如，具有相似和基本上并行的路由），但具有显着不同的信号传播速度特性。 例如，这种双形互连资源的主要或更大部分可以具有所谓的正常信号速度，而较小次要部分可具有明显更快的信号速度。 辅助（例如时钟和清除）信号分布也可以被增强，并且因此也可以是设备上的相邻或附近逻辑模块之间的输入/输出电路和级联连接。

公开(公告)号：US6005688A

公开(公告)日：1999-12-21

申请号：US103464

申请日：1998-06-23

Applicant: Ming-Mu Hsieh ,  Shi-Zheng Kuo ,  Wei-Jen Huang

Inventor： Ming-Mu Hsieh ,  Shi-Zheng Kuo ,  Wei-Jen Huang

IPC: H04N1/00 ,  H04N1/46

CPC classification number: H04N1/00816 ,  H04N1/00795 ,  H04N1/00822

Abstract: A batch scanning method for an image input system includes sorting a plurality of image areas according to top positions of said image areas. A calibration mode is set. Next, top, bottom, left and right positions of the present image area, and the top position of the next higher image area are set to some registers. Thereafter, the image input system is calibrated when the present image area is the highest image area of the sorted areas. Then, the present image area is scanned. Afterward, a light source and a photodetector are moved to the top position of said next higher image area when at least one image area has not been scanned. The position setting step, the scanning step and the moving step are repeated until the lowest image area has been scanned.

Abstract translation: 用于图像输入系统的批量扫描方法包括根据所述图像区域的顶部位置对多个图像区域进行分类。 设置校准模式。 接下来，将当前图像区域的顶部，底部，左侧和右侧位置以及下一个较高图像区域的顶部位置设置为一些寄存器。 此后，当当前图像区域是分类区域的最高图像区域时，图像输入系统被校准。 然后，扫描当前图像区域。 之后，当至少一个图像区域未被扫描时，光源和光电检测器被移动到所述下一较高图像区域的顶部位置。 重复位置设定步骤，扫描步骤和移动步骤，直到扫描最低图像区域为止。