公开(公告)号：US06633838B1

公开(公告)日：2003-10-14

申请号：US09435071

申请日：1999-11-04

申请人： Lakshminarayana Baba Arimilli ,  Michael Stephen Floyd ,  Larry Scott Leitner ,  Kevin F. Reick ,  Jennifer Lane Vargus

发明人： Lakshminarayana Baba Arimilli ,  Michael Stephen Floyd ,  Larry Scott Leitner ,  Kevin F. Reick ,  Jennifer Lane Vargus

IPC分类号： G06F1125

CPC分类号： G06F11/2236

摘要： The system and method of the present invention is embodied in a multi-state on-chip logic analyzer that is preferably integrated into a VLSI circuit. In general, the logic analyzer is preferably coupled to a multilevel trace array for storing event trace data generated by the logic analyzer. Input and output logic coupled to both the trace array and the logic analyzer allows reading or writing from or to the trace array, and programming of trigger and condition criteria for transitioning states within the logic analyzer. The logic analyzer has the capability match one or more programmable trigger events to satisfy one or more programmable conditions. Further, the logic analyzer preferably has the capability to initialize programmable conditions in desired states, and to store event trace data in an on-chip array for trace data reconstruction and analysis. Trace array input and output logic allows reading or writing from or to the trace array, and programming of trigger and condition criteria for transitioning states within the logic analyzer. Further, the trace array input and output logic is preferably accessible at both the wafer and component stage to allow for testing and debugging of the VLSI circuitry.

摘要翻译： 本发明的系统和方法体现在优选集成到VLSI电路中的多状态片上逻辑分析仪中。 通常，逻辑分析器优选地耦合到多级跟踪阵列，用于存储由逻辑分析器生成的事件跟踪数据。 耦合到跟踪阵列和逻辑分析仪的输入和输出逻辑器允许从跟踪数组读取或写入数据，以及对逻辑分析器内的转换状态的触发和条件标准进行编程。 逻辑分析仪具有匹配一个或多个可编程触发事件的能力，以满足一个或多个可编程条件。 此外，逻辑分析器优选地具有在期望状态下初始化可编程条件的能力，并且将事件跟踪数据存储在用于跟踪数据重建和分析的片上阵列中。 跟踪数组输入和输出逻辑允许从跟踪数组读取或写入数据，以及对逻辑分析器内的转换状态的触发和条件标准进行编程。 此外，迹线阵列输入和输出逻辑优选在晶片和元件级可访问以允许对VLSI电路进行测试和调试。

公开(公告)号：US07725685B2

公开(公告)日：2010-05-25

申请号：US12033385

申请日：2008-02-19

申请人： Michael Stephen Floyd ,  Larry Scott Leitner

发明人： Michael Stephen Floyd ,  Larry Scott Leitner

IPC分类号： G06F9/30

CPC分类号： G06F9/3851 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/3842 ,  G06F9/3867 ,  G06F11/0715 ,  G06F11/0721 ,  G06F11/0757 ,  G06F11/1407

摘要： Monitoring is performed to detect a hang condition. A timer is set to detect a hang based on a core hang limit. If a thread hangs for the duration of the core hang limit, then a core hang is detected. If the thread is performing an external memory transaction, then the timer is increased to a longer memory hang limit. If the thread is waiting for a shared resource, then the timer may be increased to the longer memory hang limit if another thread or, more particularly, the thread blocking the resource has a pending memory transaction. Responsive to detecting a hang condition, instructions dispatched to the plurality of execution units may be flushed, or the processor may be reset and restored to a previously known good, checkpointed architected state.

摘要翻译： 执行监视以检测挂起状况。 一个定时器被设置为基于核心挂起限制来检测挂起。 如果线程在核心挂起限制的持续时间内挂起，则会检测到核心挂起。 如果线程正在执行外部存储器事务，则定时器增加到更长的内存挂起限制。 如果线程正在等待共享资源，则如果另一个线程，更具体地说，阻塞资源的线程具有未决的存储器事务，则定时器可​​能会增加到更长的内存挂起限制。 响应于检测挂起状况，可以刷新发送到多个执行单元的指令，或者可以将处理器复位并恢复到先前已知的良好的，检查点的架构状态。

公开(公告)号：US06393594B1

公开(公告)日：2002-05-21

申请号：US09372698

申请日：1999-08-11

申请人： Carl J. Anderson ,  Michael Stephen Floyd ,  Larry Scott Leitner ,  Bradley McCredie ,  Kevin Franklin Reick ,  Jennifer Lane Vargus

发明人： Carl J. Anderson ,  Michael Stephen Floyd ,  Larry Scott Leitner ,  Bradley McCredie ,  Kevin Franklin Reick ,  Jennifer Lane Vargus

IPC分类号： G06F1100

CPC分类号： G01R31/318385 ,  G01R31/3183

摘要： A method and system for testing an integrated circuit. A test substrate is provided which is manufactured by the same particular production technology for which the integrated circuit is designed. A pattern generator for generating test data and a result checker for comparing output data are embedded on the test substrate. Isolated portions of circuitry of the integrated circuit are selectively embedded onto the test substrate. Test data from the pattern generator is applied to the isolated portions of circuitry under a first operating condition. The data output from the isolated portions of circuitry is selectively recorded into the result checker. The isolated portions of circuitry are then subjected to testing by applying test data from the pattern generator to the isolated portions of circuitry under a second operating condition. Errors in the isolated portions of circuitry are detected with the result checker by comparing data output from the isolated portions of circuitry with the selectively recorded data output, such that the integrated circuit is tested by subsets, independently of testing the integrated circuit in its entirety.

摘要翻译： 一种用于测试集成电路的方法和系统。 提供了通过设计集成电路的相同特定制造技术制造的测试基板。 用于产生测试数据的图形发生器和用于比较输出数据的结果检查器嵌入在测试基板上。 集成电路的电路的隔离部分选择性地嵌入到测试基板上。 来自图案发生器的测试数据被应用于在第一操作条件下的电路的隔离部分。 从电路的隔离部分输出的数据被选择性地记录到结果检查器中。 然后通过在第二操作条件下将来自图案发生器的测试数据应用到电路的隔离部分来对电路的隔离部分进行测试。 通过将来自电路的隔离部分的输出的数据与选择性记录的数据输出进行比较来检测电路的隔离部分中的错误，使得集成电路被子集测试，独立于集成电路的整体测试。

公开(公告)号：US06802031B2

公开(公告)日：2004-10-05

申请号：US09864114

申请日：2001-05-24

申请人： Michael Stephen Floyd ,  Larry Scott Leitner ,  Kevin F. Reick

发明人： Michael Stephen Floyd ,  Larry Scott Leitner ,  Kevin F. Reick

IPC分类号： G06F1100

CPC分类号： G06F11/366 ,  G06F11/3466 ,  G06F11/348 ,  G06F11/3636 ,  G06F2201/835 ,  G06F2201/86 ,  G06F2201/88

摘要： A trace array for recording states of signals includes N-storage locations for k trace signals. In the write mode, an address generator combines the outputs of an event signal counter and a cycle clock counter to generate trace array addresses. A start code is written each time an event signal occurs and event addresses are saved. Recording is stopped by a stop signal and the stop address is saved. A compression code and time stamp code are written when no state changes occur in any trace signals at the cycle clock times to compress recorded trace signal data. An output processor reads out stored states of the trace signals and uses the start codes, event addresses, stop address, compression code and time stamp to reconstruct the original trace signal sequences for analysis.

摘要翻译： 用于记录信号状态的迹线阵列包括用于k个跟踪信号的N个存储位置。 在写模式下，地址生成器将事件信号计数器和周期时钟计数器的输出相结合，生成跟踪数组地址。 每次发生事件信号时写入起始码，并保存事件地址。 通过停止信号停止录像，并保存停止地址。 当在周期时钟时间的任何跟踪信号中没有状态变化时，压缩码和时间戳码被写入，以压缩记录的跟踪信号数据。 输出处理器读出跟踪信号的存储状态，并使用起始码，事件地址，停止地址，压缩码和时间戳重建原始跟踪信号序列进行分析。

公开(公告)号：US06543003B1

公开(公告)日：2003-04-01

申请号：US09436106

申请日：1999-11-08

申请人： Michael Stephen Floyd ,  James Allan Kahle ,  Hung Qui Le ,  Larry Scott Leitner ,  Kevin Franklin Reick

发明人： Michael Stephen Floyd ,  James Allan Kahle ,  Hung Qui Le ,  Larry Scott Leitner ,  Kevin Franklin Reick

IPC分类号： G06F1100

CPC分类号： G06F9/3885 ,  G06F9/3861 ,  G06F11/0757 ,  G06F11/1405

摘要： A method and apparatus for recovering from a hang condition in a processor having a plurality of execution units. Monitoring is performed to detect a hang condition. Responsive to detecting a hang condition, instructions dispatched to the plurality of execution units are flushed.

摘要翻译： 一种用于在具有多个执行单元的处理器中从挂起状态恢复的方法和装置。 执行监视以检测挂起状况。 响应于检测挂起状况，分配给多个执行单元的指令被刷新。

公开(公告)号：US20080209134A1

公开(公告)日：2008-08-28

申请号：US12114049

申请日：2008-05-02

申请人： James Stephen Fields ,  Michael Stephen Floys ,  Paul Frank Lecocq ,  Larry Scott Leitner ,  Kevin Franklin Reick

发明人： James Stephen Fields ,  Michael Stephen Floys ,  Paul Frank Lecocq ,  Larry Scott Leitner ,  Kevin Franklin Reick

IPC分类号： G06F12/08

CPC分类号： G06F9/3885 ,  G06F9/30003 ,  G06F9/30101 ,  G06F9/30181 ,  G06F12/0888

摘要： In a multiprocessor environment, by executing cache-inhibited reads or writes to registers, a scan communication is used to rapidly access registers inside and outside a chip originating the command. Cumbersome locking of the memory location may be thus avoided. Setting of busy latches at the outset virtually eliminates the chance of collisions, and status bits are set to inform the requesting core processor that a command is done and free of error, if that is the case.

摘要翻译： 在多处理器环境中，通过对寄存器执行高速缓存禁止读或写操作，使用扫描通信来快速访问发起命令的芯片内外的寄存器。 因此可以避免存储器位置的繁琐的锁定。 一开始就设置忙锁实际上消除了冲突的机会，并且设置状态位以通知请求的核心处理器完成命令并且没有错误，如果是这样的话。

公开(公告)号：US08271738B2

公开(公告)日：2012-09-18

申请号：US12114049

申请日：2008-05-02

申请人： James Stephen Fields, Jr. ,  Michael Stephen Floys ,  Paul Frank Lecocq ,  Larry Scott Leitner ,  Kevin Franklin Reick

发明人： James Stephen Fields, Jr. ,  Michael Stephen Floys ,  Paul Frank Lecocq ,  Larry Scott Leitner ,  Kevin Franklin Reick

IPC分类号： G06F12/00

CPC分类号： G06F9/3885 ,  G06F9/30003 ,  G06F9/30101 ,  G06F9/30181 ,  G06F12/0888

摘要： In a multiprocessor environment, by executing cache-inhibited reads or writes to registers, a scan communication is used to rapidly access registers inside and outside a chip originating the command. Cumbersome locking of the memory location may be thus avoided. Setting of busy latches at the outset virtually eliminates the chance of collisions, and status bits are set to inform the requesting core processor that a command is done and free of error, if that is the case.

摘要翻译： 在多处理器环境中，通过对寄存器执行高速缓存禁止读或写操作，使用扫描通信来快速访问发起命令的芯片内外的寄存器。 因此可以避免存储器位置的繁琐的锁定。 一开始就设置忙锁实际上消除了冲突的机会，并且设置状态位以通知请求的核心处理器完成命令并且没有错误，如果是这样的话。