公开(公告)号：US11256520B2

公开(公告)日：2022-02-22

申请号：US16574956

申请日：2019-09-18

Applicant: Xilinx, Inc.

Inventor： David P. Schultz ,  Adrian M. Hernandez ,  David Robinson ,  Elessar Taggart ,  Max Heimer

IPC: G06F11/00 ,  G06F9/445 ,  G06F11/07

Abstract: Tracing status of a programmable device can include, in response to loading a device image for the programmable device, determining, using a processing unit on the programmable device, trace data for the device image, storing, by the processing unit, the trace data for the device image in a memory, and, in response to unloading the device image, recording the unloading of the device image in the trace data in the memory.

公开(公告)号：US11169822B2

公开(公告)日：2021-11-09

申请号：US16276178

申请日：2019-02-14

Applicant: Xilinx, Inc.

Inventor： Rafael C. Camarota ,  David P. Schultz

IPC: G06F9/445 ,  G06F13/40

Abstract: Examples described herein provide for an integrated circuit (IC) having a programmable logic region that is capable of being configured via a programmable network. In an example, an IC includes a programmable logic region, a controller, and a programmable network. The programmable network is connected between the controller and the programmable logic region. The controller is programmed to configure the programmable logic region via the programmable network. In some examples, the programmable logic region can be configured faster, among other benefits.

公开(公告)号：US10893005B2

公开(公告)日：2021-01-12

申请号：US16133357

申请日：2018-09-17

Applicant: Xilinx, Inc.

Inventor： David P. Schultz ,  Ian A. Swarbrick ,  Jun Liu ,  Raymond Kong ,  Herve Alexanian

IPC: H04L12/931 ,  G06F15/78 ,  H04L12/933 ,  H04L12/761

Abstract: Examples described herein provide for an electronic circuit, such as a System-on-Chip (SoC), having a Network-on-Chip (NoC). The NoC is configurable and has capabilities to be partially reconfigured. In an example, a NoC on an integrated circuit is configured. Subsystems on the integrated circuit communicate via the NoC. The NoC is partially reconfigured. A first subset of the NoC is reconfigured during the partial reconfiguration, and a second subset of the NoC is capable of continuing to pass communications uninterruptedly during the partial reconfiguration. After the partial reconfiguration, two or more of the subsystems communicate via the first subset of the NoC.

公开(公告)号：US10541686B1

公开(公告)日：2020-01-21

申请号：US16192053

申请日：2018-11-15

Applicant: Xilinx, Inc.

Inventor： David P. Schultz ,  David Robinson ,  Kusuma Bathala ,  Wenyi Song

IPC: H03K19/177

Abstract: A circuit for routing data in an integrated circuit device is described. The circuit comprises an input/output port; an interface circuit coupled to the input/output port and configured to receive data, the interface circuit comprising a selection circuit enabling the selection of the data and a predetermined value; and a control circuit coupled to control the selection circuit; wherein the control circuit holds the input/output port at the predetermined value during a partial reconfiguration of the integrated circuit device in response to a control signal. A method of configuring a circuit for routing data in an integrated circuit device is also described.

公开(公告)号：US12124323B2

公开(公告)日：2024-10-22

申请号：US17883379

申请日：2022-08-08

Applicant: XILINX, INC.

Inventor： Ahmad R. Ansari ,  David P. Schultz ,  Felix Burton ,  Jeffrey Cuppett

IPC: G06F11/07 ,  G06F9/30

CPC classification number: G06F11/0763 ,  G06F9/30101 ,  G06F11/0772

Abstract: Embodiments herein describe integrity check techniques that are efficient and flexible by using local registers in a segment to store check values which can be used to detect errors in the local configuration data in the same segment. In addition to containing local registers storing the check values, each segment can include a mask register indicated which of the configuration registers should be checked and which can be ignored. Further, the segments can include a next segment register indicating the next segment the check engine should evaluate for errors.

公开(公告)号：US12056505B2

公开(公告)日：2024-08-06

申请号：US17862257

申请日：2022-07-11

Applicant: XILINX, INC.

Inventor： Ahmad R. Ansari ,  David P. Schultz

IPC: G06F15/177 ,  G06F9/00 ,  G06F9/24 ,  G06F9/445

CPC classification number: G06F9/44505

Abstract: Embodiments herein describe a distributed configuration system for a configurable device. Instead of relying solely on a central configuration manager to distribute configuration information to various subsystems in the device, the embodiments herein include configuration interface managers (CIM) that are distributed in different regions of the device, whether those regions are in one integrated circuit or include multiple integrated circuits. The embodiments can still use a central configuration manager to distribute configuration information in a device image to the plurality of CIMs, which can then forward the configuration information to their assigned regions.

公开(公告)号：US10963170B2

公开(公告)日：2021-03-30

申请号：US16262420

申请日：2019-01-30

Applicant: Xilinx, Inc.

Inventor： Subodh Kumar ,  David P. Schultz ,  Weiguang Lu ,  Michelle Zeng

IPC: G06F3/06

Abstract: Embodiments herein describe a reconfigurable integrated circuit (IC) where data can be retained in memory when performing a partial reconfiguration. Partial reconfiguration includes reconfiguring programmable logic in the IC while certain functions of the IC remain operational or active. In one embodiment, the reconfigurable IC includes control logic for saving or retaining data in the IC during a partial reconfiguration. That is, rather than clearing the memory elements, the user can specify that the memory blocks containing certain data should be retained while the other memory blocks can be cleared. In this manner, the data can be retained in the IC during a partial reconfiguration which saves time, power, and cost. Once partial reconfiguration is complete, the newly configured programmable logic can retrieve and process the saved data from the on-chip memory.

公开(公告)号：US20200264901A1

公开(公告)日：2020-08-20

申请号：US16276178

申请日：2019-02-14

Applicant: Xilinx, Inc.

Inventor： Rafael C. Camarota ,  David P. Schultz

IPC: G06F9/445 ,  G06F13/40

Abstract: Examples described herein provide for an integrated circuit (IC) having a programmable logic region that is capable of being configured via a programmable network. In an example, an IC includes a programmable logic region, a controller, and a programmable network. The programmable network is connected between the controller and the programmable logic region. The controller is programmed to configure the programmable logic region via the programmable network. In some examples, the programmable logic region can be configured faster, among other benefits.

公开(公告)号：US09722613B1

公开(公告)日：2017-08-01

申请号：US14867461

申请日：2015-09-28

Applicant: Xilinx, Inc.

Inventor： David P. Schultz ,  Weiguang Lu ,  Paige A. Kolze

IPC: H03K19/177

CPC classification number: H03K19/17756 ,  H03K19/17728 ,  H03K19/1774

Abstract: A circuit arrangement for enabling a partial reconfiguration of a circuit implemented in an integrated circuit device is described. The circuit arrangement comprises a plurality of circuit blocks, wherein each circuit block is configurable to implement a predetermined function and comprises a control circuit configured to receive a global enable signal and a plurality of global reconfiguration signals; and a routing network coupled to the plurality of circuit blocks for routing the global enable signal and the plurality of global reconfiguration signals to each circuit block of the plurality of circuit blocks; wherein each circuit block of the plurality of circuit blocks is configured to independently receive a local enable signal enabling a partial reconfiguration of the circuit in response to the plurality of global reconfiguration signals.