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    Selection of logic paths for redundancy
    12.
    发明授权
    Selection of logic paths for redundancy 有权
    选择冗余的逻辑路径

    公开(公告)号：US09484919B1

    公开(公告)日：2016-11-01

    申请号：US14266547

    申请日：2014-04-30

    Applicant: Xilinx, Inc.

    Inventor： Praful Jain ,  Pierre Maillard ,  James Karp ,  Michael J. Hart

    IPC: H03K19/003

    CPC classification number: H03K19/00392

    Abstract: Approaches are disclosed for processing a circuit design to protect against single event upsets. A logic path of the circuit design is selected for redundancy based on a total of failure rates of circuit elements in the logic path being greater than a product of a target reduction in failure rate of the logic path and a failure rate of a voting circuit. The circuit design is modified to include at least three instances of the logic path coupled in parallel and a voting circuit coupled to receive output signals from the instances of the logic path. The modified circuit design is stored in a memory.

    Abstract translation: 公开了用于处理电路设计以防止单个事件扰乱的方法。 基于逻辑路径中的电路元件的故障率的总和大于逻辑路径的故障率的目标降低与投票电路的故障率的乘积的总和，选择电路设计的逻辑路径用于冗余。 电路设计被修改为包括并联耦合的逻辑路径的至少三个实例和耦合以从逻辑路径的实例接收输出信号的投票电路。 修改后的电路设计存储在存储器中。

    Single event upset enhanced architecture
    13.
    发明授权
    Single event upset enhanced architecture 有权
    单事件加剧架构

    公开(公告)号：US09054684B1

    公开(公告)日：2015-06-09

    申请号：US13848689

    申请日：2013-03-21

    Applicant: Xilinx, Inc.

    Inventor： Santosh Kumar Sood ,  Praful Jain ,  Ramakrishna K. Tanikella

    IPC: H03K5/125 ,  G01R31/3181

    CPC classification number: H03K5/125 ,  G01R31/31816 ,  G01R31/318519

    Abstract: A circuit block within an integrated circuit includes a multiplexor (225, 625) configured to pass either a first signal or a second signal, wherein the first signal is independent of the second signal. The circuit block further includes a first flip-flop (210, 610) configured to receive an output of the multiplexor and a second flip-flop (215, 615) configured to receive the second signal. In a first mode of operation, the multiplexor passes the first signal to the first flip-flop. Further, the first flip flop and the second flip-flop operate independently of one another. In a second mode of operation, the multiplexor passes the second signal to the first flip-flop. Further, the first flip-flop and the second flip-flop both receive the second signal.

    Abstract translation: 集成电路内的电路块包括经配置以通过第一信号或第二信号的多路复用器（225,625），其中第一信号独立于第二信号。 电路块还包括被配置为接收多路复用器的输出的第一触发器（210,610）和被配置为接收第二信号的第二触发器（215,615）。 在第一操作模式中，多路复用器将第一信号传递到第一触发器。 此外，第一触发器和第二触发器彼此独立地操作。 在第二操作模式中，多路复用器将第二信号传递到第一触发器。 此外，第一触发器和第二触发器都接收第二信号。

    Power delivery network for active-on-active stacked integrated circuits
    14.
    发明授权
    Power delivery network for active-on-active stacked integrated circuits 有权

    公开(公告)号：US11270977B2

    公开(公告)日：2022-03-08

    申请号：US16679063

    申请日：2019-11-08

    Applicant: XILINX, INC.

    Inventor： Praful Jain ,  Steven P. Young ,  Martin L. Voogel ,  Brian C. Gaide

    IPC: H01L25/065 ,  H01L25/00

    Abstract: An apparatus includes a first die including a first substrate with first TSVs running through it, a first top metal layer and first chimney stack vias (CSVs) connecting the first TSVs with the first top metal layer. The apparatus further includes an uppermost die including an uppermost substrate and an uppermost top metal layer, and uppermost CSVs connecting the uppermost substrate with the uppermost top metal layer. The first and uppermost dies are stacked face to face, the first TSVs and the first CSVs are mutually aligned, and the dies are configured such that current is delivered to the apparatus from the first TSVs up through the first CSVs, the first and uppermost top metal layers, and the uppermost CSVs.

    Forming and/or configuring stacked dies
    15.
    发明授权
    Forming and/or configuring stacked dies 有权

    公开(公告)号：US11043480B1

    公开(公告)日：2021-06-22

    申请号：US16437498

    申请日：2019-06-11

    Applicant: XILINX, INC.

    Inventor： Praful Jain ,  Martin Voogel ,  Brian Gaide

    IPC: H01L25/00 ,  H01L21/66 ,  H01L25/065

    Abstract: Examples described herein generally relate to forming and/or configuring a die stack in a multi-chip device. An example is a method of forming a multi-chip device. Dies are formed. At least two or more of the dies are interchangeable. Characteristics of the at least two or more of the dies that are interchangeable are determined. A die stack comprising the at least two or more of the dies that are interchangeable is formed. Respective placements within the die stack of the at least two or more of the dies that are interchangeable are based on the characteristics.

    Circuit for and method of preventing multi-bit upsets induced by single event transients
    16.
    发明授权
    Circuit for and method of preventing multi-bit upsets induced by single event transients 有权

    公开(公告)号：US09825632B1

    公开(公告)日：2017-11-21

    申请号：US15228981

    申请日：2016-08-04

    Applicant: Xilinx, Inc.

    Inventor： Pierre Maillard ,  Michael J. Hart ,  Praful Jain ,  Robert I. Fu

    IPC: H03K19/003 ,  H03K19/177

    CPC classification number: H03K19/00315 ,  H03K19/17728 ,  H03K19/1776

    Abstract: A circuit for preventing multi-bit upsets induced by single event transients is described. The circuit comprises a clock generator configured to generate a first clock signal and a second clock signal; a first memory element configured to receive a first input signal and generate a first output signal, the first memory element having a first clock input configured to receive the first clock signal; and a second memory element configured to receive the first output signal and generate a second output signal, the second memory element having a second clock input configured to receive the second clock signal; wherein the first clock signal is the same as the second clock signal. A method of preventing multi-bit upsets induced by single event transients is also described.

    INTERCONNECT CIRCUITS HAVING LOW THRESHOLD VOLTAGE P-CHANNEL TRANSISTORS FOR A PROGRAMMABLE INTEGRATED CIRCUIT
    17.
    发明申请
    INTERCONNECT CIRCUITS HAVING LOW THRESHOLD VOLTAGE P-CHANNEL TRANSISTORS FOR A PROGRAMMABLE INTEGRATED CIRCUIT 有权
    具有可编程集成电路的低阈值电压P沟道晶体管的互连电路

    公开(公告)号：US20160049940A1

    公开(公告)日：2016-02-18

    申请号：US14458017

    申请日：2014-08-12

    Applicant: Xilinx, Inc.

    Inventor： Praful Jain ,  Michael J. Hart

    IPC: H03K19/0185 ,  H01L27/118 ,  H03K19/177

    CPC classification number: H03K19/018571 ,  H01L27/11803 ,  H03K19/1737 ,  H03K19/17736 ,  H03K19/1776

    Abstract: An exemplary interconnect circuit for a programmable integrated circuit (IC) includes an input terminal coupled to receive from a node in the programmable IC, an output terminal coupled to transmit towards another node in the programmable IC, first and second control terminals coupled to receive from a memory cell of the programmable IC, and a complementary metal oxide semiconductor (CMOS) pass-gate coupled between the input terminal and the output terminal and to the first and second control terminals. The CMOS pass-gate includes a P-channel transistor configured with a low threshold voltage for a CMOS process used to fabricate the programmable IC.

    Abstract translation: 用于可编程集成电路（IC）的示例性互连电路包括耦合以从可编程IC中的节点接收的输入端子，耦合到朝向可编程IC中的另一节点发送的输出端子，耦合以从可编程集成电路 可编程IC的存储单元和耦合在输入端子和输出端子之间的互补金属氧化物半导体（CMOS）通过栅极以及耦合到第一和第二控制端子。 CMOS通过栅极包括配置有用于制造可编程IC的CMOS工艺的低阈值电压的P沟道晶体管。

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