公开(公告)号：US20080001255A1

公开(公告)日：2008-01-03

申请号：US11845348

申请日：2007-08-27

申请人： Takashi OKUDA ,  Yasuo Morimoto ,  Yuko Maruyama ,  Toshio Kumamoto

发明人： Takashi OKUDA ,  Yasuo Morimoto ,  Yuko Maruyama ,  Toshio Kumamoto

IPC分类号： H01L29/00

CPC分类号： H01L23/5223 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.

摘要翻译： 半导体器件包括：包括主表面的半导体衬底; 多个第一互连形成在形成在主表面上并沿预定方向延伸的电容形成区域中; 多个第二互连，每个相邻于位于电容形成区域的边缘处的第一互连，沿预定方向延伸并具有固定电位; 以及绝缘层，形成在主表面上，并且填充在每个第一互连之间以及第一互连和第二互连之间相邻。 第一互连和第二互连在平行于主表面的平面中以基本相等的间隔定位，并且被定位成在基本上垂直于预定方向的方向上对齐。

公开(公告)号：US06573588B1

公开(公告)日：2003-06-03

申请号：US10278943

申请日：2002-10-24

申请人： Toshio Kumamoto ,  Takashi Okuda ,  Yasuo Morimoto

发明人： Toshio Kumamoto ,  Takashi Okuda ,  Yasuo Morimoto

IPC分类号： H01L2900

CPC分类号： H01L29/92 ,  H01L29/94

摘要： A P well region formed on a buried N well region and a n+ active region that are connected each other through a lead wire, serve as one terminal T1, and a gate electrode and a buried N well region that are connected each other through a leading N well region and a lead wire, serve as the other terminal T2. Thereby, the voltage dependence of capacitance C1 formed between the gate electrode and the n+ active region is canceled out with the voltage dependence of capacitance C2 formed between the P well region and the buried N well region.

摘要翻译： AP阱区域形成在通过引线彼此连接的掩埋N阱区域和n +有源区域上，用作一个端子T1，以及通过前导N相互连接的栅电极和掩埋N阱区域 井区和导线，作为另一个终端T2。 由此，在P阱区域和掩埋N阱区域之间形成的电容C2的电压依赖性抵消在栅电极和n +有源区域之间形成的电容C1的电压依赖性。

公开(公告)号：US4039615A

公开(公告)日：1977-08-02

申请号：US644923

申请日：1975-12-29

申请人： Yasuie Mikami ,  Ippo Takei ,  Kazuo Soma ,  Yasuo Morimoto

发明人： Yasuie Mikami ,  Ippo Takei ,  Kazuo Soma ,  Yasuo Morimoto

IPC分类号： C01F7/74 ,  C30B7/00 ,  B01D9/02

CPC分类号： C01F7/748 ,  C01F7/746 ,  C30B29/10 ,  C30B7/00

摘要： Hexagonal plate crystals of aluminum sulfate are produced in chemically pure form by a process which comprises cooling a heated saturated solution of chemically impure aluminum sulfate acidified with sulfuric acid to precipitate crystals of aluminum sulfate, heating the slurry of the cooled solution containing the precipitated aluminum sulfate crystals to a predetermined temperature wherein the temperature is maintained for a time sufficient to dissolve a portion of the crystals in the solution, cooling the heated slurry to precipitate aluminum sulfate crystals, and separating the precipitated crystals from the slurry.

摘要翻译： 硫酸铝的六角板晶体通过包括冷却用硫酸酸化的化学不纯的硫酸铝的加热饱和溶液来沉淀硫酸铝晶体的方法以化学纯的形式生产，加热含有沉淀的硫酸铝的冷却溶液的浆液 晶体到预定温度，其中保持温度足以溶解溶液中的一部分晶体的时间，冷却加热的浆料以沉淀硫酸铝晶体，并将沉淀的晶体与浆料分离。

公开(公告)号：US07276776B2

公开(公告)日：2007-10-02

申请号：US11013514

申请日：2004-12-17

申请人： Takashi Okuda ,  Yasuo Morimoto ,  Yuko Maruyama ,  Toshio Kumamoto

发明人： Takashi Okuda ,  Yasuo Morimoto ,  Yuko Maruyama ,  Toshio Kumamoto

IPC分类号： H01L29/00

CPC分类号： H01L23/5223 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.

摘要翻译： 半导体器件包括：包括主表面的半导体衬底; 多个第一互连形成在形成在主表面上并沿预定方向延伸的电容形成区域中; 多个第二互连，每个相邻于位于电容形成区域的边缘处的第一互连，沿预定方向延伸并具有固定电位; 以及绝缘层，形成在主表面上，并且填充在每个第一互连之间以及第一互连和第二互连之间相邻。 第一互连和第二互连在平行于主表面的平面中以基本相等的间隔定位，并且被定位成在基本上垂直于预定方向的方向上对准。

公开(公告)号：US20050145987A1

公开(公告)日：2005-07-07

申请号：US11013514

申请日：2004-12-17

申请人： Takashi Okuda ,  Yasuo Morimoto ,  Yuko Maruyama ,  Toshio Kumamoto

发明人： Takashi Okuda ,  Yasuo Morimoto ,  Yuko Maruyama ,  Toshio Kumamoto

IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L21/822 ,  H01L23/52 ,  H01L23/522 ,  H01L27/04 ,  H01L29/76

CPC分类号： H01L23/5223 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.

摘要翻译： 半导体器件包括：包括主表面的半导体衬底; 多个第一互连形成在形成在主表面上并沿预定方向延伸的电容形成区域中; 多个第二互连，每个相邻于位于电容形成区域的边缘处的第一互连，沿预定方向延伸并具有固定电位; 以及绝缘层，形成在主表面上，并且填充在每个第一互连之间以及第一互连和第二互连之间相邻。 第一互连和第二互连在平行于主表面的平面中以基本相等的间隔定位，并且被定位成在基本上垂直于预定方向的方向上对齐。

公开(公告)号：US06734814B2

公开(公告)日：2004-05-11

申请号：US10167460

申请日：2002-06-14

申请人： Takashi Okuda ,  Toshio Kumamoto ,  Yasuo Morimoto

发明人： Takashi Okuda ,  Toshio Kumamoto ,  Yasuo Morimoto

IPC分类号： H03M300

CPC分类号： H03M7/3006 ,  H03M3/368 ,  H03M3/418 ,  H03M3/43 ,  H03M3/45 ,  H03M3/452 ,  H03M7/3022 ,  H03M7/3028 ,  H03M7/3033 ,  H03M7/3037

摘要： In a modulator, an attenuator attenuates an input signal, a delay element gives a delay of 1 sample period to the attenuated signal, an adder subtracts a quantized signal that has been fed back with a delay of 1 sample period, from the delayed signal, two or more integrators integrate a result of the subtraction, an adder which adds outputs of the respective integrators and the attenuated signal, and a quantizer quantizes a result of the addition, outputs a result of the quantization as an output signal and feeds back the output signal to the subtractor.

摘要翻译： 在调制器中，衰减器衰减输入信号，延迟元件给衰减信号提供1个采样周期的延迟，加法器从延迟信号中减去已经以1个采样周期的延迟反馈的量化信号， 两个或更多个积分器集成减法的结果，加上各积分器的输出的加法器和衰减的信号，量化器对加法的结果进行量化，输出量化的结果作为输出信号，反馈输出 发信号给减法器。

公开(公告)号：US06323794B1

公开(公告)日：2001-11-27

申请号：US09437405

申请日：1999-11-10

申请人： Takashi Okuda ,  Toshio Kumamoto ,  Yasuo Morimoto

发明人： Takashi Okuda ,  Toshio Kumamoto ,  Yasuo Morimoto

IPC分类号： H03M300

CPC分类号： H03M7/3022 ,  H03M3/414 ,  H03M3/458 ,  H03M3/50

摘要： Modulators (M1 to Mk (k≧2)) are connected in a multi-stage such that each of quantization errors (e1, e2, . . . ) of the modulators (M1 to Mk−1) is fed to the input of the next stage modulator. Each output signal of the modulators (M2 to Mk) is fed back to the input of the immediately preceding modulator. The modulators (M1 to Mk) are all first-order modulators. Only the final stage modulator (Mk) has a multi-bit quantizer (6), and all the preceding modulators (M1 to Mk−1) have an 1-bit quantizer (3). Accordingly, a noise-shaping equal to that of a multi-bit higher-order modulator is realized on a small-scale circuit while retaining stability.

摘要翻译： 调制器（M1至Mk（k> = 2））以多级连接，使得调制器（M1至Mk-1）的每个量化误差（e1，e2，...）被馈送到 下一级调制器。 调制器（M2至Mk）的每个输出信号被反馈到紧接在前的调制器的输入端。 调制器（M1至Mk）都是一阶调制器。 只有最后级调制器（Mk）具有多位量化器（6），并且所有先前的调制器（M1至Mk-1）都具有1位量化器（3）。 因此，在保持稳定性的同时，在小规模电路上实现等于多位高阶调制器的噪声整形。

公开(公告)号：US06300890B1

公开(公告)日：2001-10-09

申请号：US09716241

申请日：2000-11-21

申请人： Takashi Okuda ,  Toshio Kumamoto ,  Yasuo Morimoto

发明人： Takashi Okuda ,  Toshio Kumamoto ,  Yasuo Morimoto

IPC分类号： H03M300

CPC分类号： H03M3/46

摘要： A delta-sigma modulator comprises a 1-bit quantizer located for quantizing an analog signal applied thereto, and for outputting a first quantized digital signal, a 1-bit DA converter converting the first quantized digital signal into a quantized analog signal, a subtracting circuit for subtracting the quantized analog signal output from the 1-bit DA converter from the analog signal input to the 1-bit quantizer, and an input integrating circuit series including a series of one or more stages each of which includes a subtracter and an integrator for integrating an output of the subtracter, one subtracter at a first stage subtracting the quantized analog signal delayed by a delay element from an input analog signal input to the delta-sigma modulator, and one integrator at a final stage outputting its output to the 1-bit quantizer. A multiple-bit quantizer quantizes an analog output of the subtracting circuit and outputs a second quantized digital signal. A differentiator then calculates an Nth-order derivative of the second quantized digital signal from the multiple-bit quantizer, N being equal to a number of the one or more stages included in the input integrating circuit series, and an adder adds an output of the differentiator to the first quantized digital signal from the 1-bit quantizer.

摘要翻译： Δ-Σ调制器包括1位量化器，用于量化施加到其上的模拟信号，并用于输出第一量化数字信号，将第一量化数字信号转换为量化模拟信号的1位DA转换器，减法电路 用于从输入到1位量化器的模拟信号中减去从1位DA转换器输出的量化模拟信号，以及包括一系列一级或多级的输入积分电路系列，每级包括减法器和积分器 对减法器的输出进行积分，一个减法器在第一级从输入到Δ-Σ调制器的输入模拟信号中减去由延迟元件延迟的量化模拟信号，以及一个积分器，将其输出输出到1- 位量化器。 多位量化器量化减法电路的模拟输出并输出第二量化数字信号。 然后，微分器计算来自多位量化器的第二量化数字信号的N次导数，N等于包括在输入积分电路序列中的一个或多个级的数，并且加法器将 与1位量化器的第一个量化数字信号进行微分。

公开(公告)号：US5972507A

公开(公告)日：1999-10-26

申请号：US998037

申请日：1997-12-23

申请人： Yasuo Morimoto ,  Noriaki Tsukida ,  Hiroshi Saga ,  Hidenao Saito

发明人： Yasuo Morimoto ,  Noriaki Tsukida ,  Hiroshi Saga ,  Hidenao Saito

IPC分类号： G01N33/548 ,  B01J20/281 ,  C08B9/00 ,  C08B16/00 ,  C08J3/14 ,  C08L1/00 ,  G01N30/88 ,  C08B15/00

CPC分类号： C08J3/14 ,  C08B16/00 ,  C08J2301/02 ,  Y10T428/2982

摘要： A method for producing cellulose beads which are high in sphericity and narrow in bead size distribution. Cellulose beads are produced by supplying a cellulose solution into a rotating vessel which is rotated at high speed by a rotary shaft and has outlets such as small holes and nozzles, flying droplets formed under a centrifugal acceleration of 10 to 1000 G through the outlets that have a diameter of 0.1 to 5.0 mm, and capturing the droplets with a coagulating solution to coagulate the droplets.

摘要翻译： 一种球形度高，珠粒分布窄的纤维素珠粒的制造方法。 纤维素珠通过将纤维素溶液供给到通过旋转轴高速旋转的旋转容器中并且具有诸如小孔和喷嘴的出口，通过具有10至1000G的离心加速度形成的飞沫，通过具有 直径为0.1至5.0mm，并用凝固溶液捕获液滴以使液滴凝结。

公开(公告)号：US20110140277A1

公开(公告)日：2011-06-16

申请号：US13030861

申请日：2011-02-18

申请人： Takashi OKUDA ,  Yasuo Morimoto ,  Yuko Maruyama ,  Toshio Kumamoto

发明人： Takashi OKUDA ,  Yasuo Morimoto ,  Yuko Maruyama ,  Toshio Kumamoto

IPC分类号： H01L23/522

CPC分类号： H01L23/5223 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.

摘要翻译： 半导体器件包括：包括主表面的半导体衬底; 多个第一互连形成在形成在主表面上并沿预定方向延伸的电容形成区域中; 多个第二互连，每个相邻于位于电容形成区域的边缘处的第一互连，沿预定方向延伸并具有固定电位; 以及绝缘层，形成在主表面上，并且填充在每个第一互连之间以及第一互连和第二互连之间相邻。 第一互连和第二互连在平行于主表面的平面中以基本相等的间隔定位，并且被定位成在基本上垂直于预定方向的方向上对齐。