公开(公告)号：US20110154000A1

公开(公告)日：2011-06-23

申请号：US12653800

申请日：2009-12-18

申请人： Joshua B. Fryman ,  Andrew Thomas Forsyth ,  Edward Grochowski

发明人： Joshua B. Fryman ,  Andrew Thomas Forsyth ,  Edward Grochowski

IPC分类号： G06F9/30 ,  G06F12/08

CPC分类号： G06F9/3004 ,  G06F9/30087

摘要： A technique to perform a fast compare-exchange operation is disclosed. More specifically, a machine-readable medium, processor, and system are described that implement a fast compare-exchange operation as well as a cache line mark operation that enables the fast compare-exchange operation.

摘要翻译： 公开了一种执行快速比较交换操作的技术。 更具体地，描述了实现快速比较交换操作以及启用快速比较交换操作的高速缓存行标记操作的机器可读介质，处理器和系统。

公开(公告)号：US07395304B2

公开(公告)日：2008-07-01

申请号：US10890848

申请日：2004-07-13

申请人： Bharat Bhushan ,  Vinod Sharma ,  Edward Grochowski ,  John Crawford

发明人： Bharat Bhushan ,  Vinod Sharma ,  Edward Grochowski ,  John Crawford

IPC分类号： G06F7/04

CPC分类号： G06F7/5095 ,  G06F7/02 ,  G06F7/4824

摘要： A method and apparatus is disclosed that uses an arithmetic circuit for adding numbers represented in a redundant form to also subtract numbers received in redundant form, including numbers received from a bypass circuit. A non-propagative comparator circuit is then used to compare a given value with a result from the arithmetic circuit to determine if the result is equal to the given value. All of the operations described above can be accomplished without propagating carry signals throughout the circuitry.The method includes generating a complemented redundant form of at least one number supplied to the arithmetic circuit in redundant form. It also includes providing adjustment input to the arithmetic circuit to augment a result produced through the arithmetic circuit. This adjustment causes the arithmetic circuit to generate a valid outcome in redundant form as a result of a subtraction operation if the arithmetic operation is subtraction. Then the result is compared to a given value using a non-propagative comparator to determine equality or inequality of the result to the given value.

摘要翻译： 公开了一种方法和装置，其使用运算电路来添加以冗余形式表示的数字，还可以减去以冗余形式接收的数字，包括从旁路电路接收的数字。 然后使用非传播比较器电路将给定值与运算电路的结果进行比较，以确定结果是否等于给定值。 可以在整个电路中不传播进位信号来实现上述所有操作。 该方法包括以冗余的形式生成提供给运算电路的至少一个数的补码冗余形式。 它还包括向算术电路提供调整输入以增加通过运算电路产生的结果。 如果算术运算是减法，则该调整使得运算电路作为减法运算的结果以冗余形式产生有效结果。 然后将结果与使用非传播比较器的给定值进行比较，以确定结果与给定值的相等或不等式。

公开(公告)号：US06954848B2

公开(公告)日：2005-10-11

申请号：US10038038

申请日：2002-01-02

申请人： Ryan Rakvic ,  Christopher Wilkerson ,  Bryan Black ,  Edward Grochowski ,  John Shen ,  Edward Brekelbaum

发明人： Ryan Rakvic ,  Christopher Wilkerson ,  Bryan Black ,  Edward Grochowski ,  John Shen ,  Edward Brekelbaum

IPC分类号： G06F9/00 ,  G06F9/30 ,  G06F9/38

CPC分类号： G06F9/3824 ,  G06F9/3836 ,  G06F9/3838

摘要： After an instruction loads data into a register at a first time, the register is monitored to see if it is read in a next clock cycle. When the data is not read in the next clock cycle, the instruction is classified as a slowable instruction. An instruction address associated with the instruction is used to update a history table. The history table stores information to indicate if an instruction is a slowable instruction or a non-slowable instruction. When the instruction address of the instruction is encountered at a second time, the history table is used to determine if the instruction is slowable or non-slowable.

摘要翻译： 在第一次指令将数据加载到寄存器中之后，监视寄存器以查看是否在下一个时钟周期读取。 当数据在下一个时钟周期内未被读取时，指令被分类为慢指令。 与指令相关联的指令地址用于更新历史表。 历史表存储用于指示指令是指令是慢指令还是非慢指令的信息。 当第二次遇到指令的指令地址时，使用历史表来确定指令是可慢还是不慢。

公开(公告)号：US08125246B2

公开(公告)日：2012-02-28

申请号：US12618629

申请日：2009-11-13

申请人： Edward Grochowski ,  Chris Wilkerson ,  Shih-Lien L. Lu ,  Murali Annavaram

发明人： Edward Grochowski ,  Chris Wilkerson ,  Shih-Lien L. Lu ,  Murali Annavaram

IPC分类号： H03K19/096

CPC分类号： G01R31/31922 ,  G01R31/31726 ,  H03K5/1534 ,  H04L7/0083 ,  H04L7/033

摘要： Two latches store the state of a data signal at a transition of a clock signal. Comparison logic compares the outputs of the two latches and produces a signal to indicate whether the outputs are equal or unequal. Systems using the latches and comparison logic are described and claimed.

摘要翻译： 两个锁存器在时钟信号的转变时存储数据信号的状态。 比较逻辑比较两个锁存器的输出，并产生一个信号以指示输出是相等还是不相等。 描述和要求保护使用锁存器和比较逻辑的系统。

公开(公告)号：US20100052730A1

公开(公告)日：2010-03-04

申请号：US12618629

申请日：2009-11-13

申请人： Edward Grochowski ,  Chris Wilkerson ,  Shih-Lien L. Lu ,  Murali Annavaram

发明人： Edward Grochowski ,  Chris Wilkerson ,  Shih-Lien L. Lu ,  Murali Annavaram

IPC分类号： H03K5/19

CPC分类号： G01R31/31922 ,  G01R31/31726 ,  H03K5/1534 ,  H04L7/0083 ,  H04L7/033

摘要： Two latches store the state of a data signal at a transition of a clock signal. Comparison logic compares the outputs of the two latches and produces a signal to indicate whether the outputs are equal or unequal. Systems using the latches and comparison logic are described and claimed.

摘要翻译： 两个锁存器在时钟信号的转变时存储数据信号的状态。 比较逻辑比较两个锁存器的输出，并产生一个信号以指示输出是相等还是不相等。 描述和要求保护使用锁存器和比较逻辑的系统。

公开(公告)号：US07480838B1

公开(公告)日：2009-01-20

申请号：US11388668

申请日：2006-03-23

申请人： Chris Wilkerson ,  Shih-Lien L. Lu ,  Edward Grochowski ,  Murali Annavaram

发明人： Chris Wilkerson ,  Shih-Lien L. Lu ,  Edward Grochowski ,  Murali Annavaram

IPC分类号： G06K5/04

CPC分类号： G06F11/0751 ,  G06F11/0724 ,  G06F11/0772 ,  G06F11/1497

摘要： Methods and systems to facilitate an efficient circuit for detecting internal timing errors for integrated devices, including a hierarchy of reporting the detection of the timing error from a circuit level to a functional unit block (FUB) level up to a global detection, and a reorder buffer (ROB) for storing a result for timing error recovery until the timing can be verified to be error free.

摘要翻译： 包括用于报告从电路电平到功能单元块（FUB）到全局检测的定时误差检测的层次结构的集成设备的检测内部定时误差的有效电路的方法和系统以及重新排序 缓冲器（ROB），用于存储用于定时错误恢复的结果，直到定时可被验证为无错误。

公开(公告)号：US20050188185A1

公开(公告)日：2005-08-25

申请号：US10783765

申请日：2004-02-20

申请人： Edward Grochowski

发明人： Edward Grochowski

IPC分类号： G06F9/00 ,  G06F9/318

CPC分类号： G06F9/30072 ,  G06F9/30145

摘要： A method and apparatus for implementing predicated instructions using selective conversion to micro-operations is presented. In one embodiment, the predicated instructions may have both a prediction of the predicate value and an indication of the confidence value of that predicted predicate value generated. When the confidence value of the prediction is low, then the predicated instruction may be decomposed into a set of micro-operations that should execute whether the predicate value is true or false. But when the confidence value is high, then the predicated instruction may be decomposed into simpler sets of micro-operations, for the cases when the predicted predicate value is true and for when it is false.

摘要翻译： 提出了一种使用选择性转换为微操作来实现预测指令的方法和装置。 在一个实施例中，所述预测指令可以具有所述谓词值的预测和所生成的所述预测谓词值的置信度值的指示。 当预测的置信度值低时，则可以将预测指令分解为应该执行谓词值是真还是假的一组微操作。 但是，当置信度值高时，对于预测的谓词值为真，以及当为假时，预测指令可能被分解成更简单的微操作集合。

公开(公告)号：US06826588B2

公开(公告)日：2004-11-30

申请号：US10032026

申请日：2001-12-17

申请人： Bharat Bhushan ,  Edward Grochowski ,  Vinod Sharma ,  John Crawford

发明人： Bharat Bhushan ,  Edward Grochowski ,  Vinod Sharma ,  John Crawford

IPC分类号： G06F702

CPC分类号： G06F7/48 ,  G06F7/02 ,  G06F7/026 ,  G06F7/4824

摘要： The present invention provides an efficient method for bypassing outputs while in redundant form to an arithmetic circuit that is capable of adding or subtracting numbers in redundant from and comparing the magnitudes of numbers received in redundant form for equality and inequality relationships. For one embodiment of the invention, an arithmetic circuit subtracts numbers received in redundant form and compares the result to zero represented in redundant form without carry propagation. In parallel with the subtraction and comparison, the most significant bits of each number received in redundant form are generated and compared for equality, and a carry-out is generated for the subtraction. These results are combined by magnitude comparison logic to produce a magnitude comparison for the numbers received in redundant form.

摘要翻译： 本发明提供了一种用于以冗余形式旁路输出到算术电路的有效方法，该算术电路能够从冗余形式中增加或减少冗余中的数字并比较用于相等和不等式关系的以冗余形式接收的数字的数量。 对于本发明的一个实施例，运算电路减去以冗余形式接收的数字，并将结果与​​以多余形式表示的零进行比较，而无需进位传播。 与减法和比较并行地，以冗余形式接收的每个数字的最高有效位被生成和比较以相等，并且为减法产生进位输出。 这些结果通过幅度比较逻辑组合，以产生以冗余形式接收的数字的幅度比较。

公开(公告)号：US06763368B2

公开(公告)日：2004-07-13

申请号：US09746940

申请日：2000-12-22

申请人： Bharat Bhushan ,  Vinod Sharma ,  Edward Grochowski ,  John Crawford

发明人： Bharat Bhushan ,  Vinod Sharma ,  Edward Grochowski ,  John Crawford

IPC分类号： G06F704

CPC分类号： G06F7/5095 ,  G06F7/02 ,  G06F7/4824

摘要： A method and apparatus for adding numbers represented in redundant form or for subtracting numbers received in redundant form and for comparing results in redundant form for equality to an expected value. A redundant arithmetic circuit performs an arithmetic operation on operands received in redundant form to generate a result represented in redundant form. A comparator circuit is coupled with the arithmetic circuit to receive the result in redundant form and to perform an equality comparison of the result to the expected value, and to indicate the truth of said equality comparison independent of carry signal propagation from the least significant digit to the most significant digit.

摘要翻译： 一种用于添加以冗余形式表示的数字或用于减去以冗余形式接收的数字并用于将用于相等的冗余形式的结果与期望值进行比较的方法和装置。 冗余算术电路对以冗余形式接收的操作数执行算术运算，以生成以冗余形式表示的结果。 比较器电路与算术电路耦合以以冗余形式接收结果，并且执行结果与期望值的相等比较，并且指示所述等式比较的真实性，独立于从最低有效数字到进位信号传播的进位信号 最重要的数字。

公开(公告)号：US5581718A

公开(公告)日：1996-12-03

申请号：US276089

申请日：1994-07-15

申请人： Edward Grochowski

发明人： Edward Grochowski

IPC分类号： G06F9/32 ,  G06F9/30 ,  G06F9/38 ,  G06F13/00

CPC分类号： G06F9/3816 ,  G06F9/30149

摘要： A method and apparatus for selecting instructions from a sequence of undifferentiated bytes of instruction data is described. A first plurality of sequential bytes of instruction data is selected from the sequence of undifferentiated bytes of instruction data. A second plurality of sequential bytes of instruction data beginning at any selected byte in the first plurality is selected from the first plurality of sequential bytes of instruction data. A third plurality of sequential bytes of instruction data beginning at any selected byte in the second plurality is selected from the second plurality of sequential bytes of instruction data. The second plurality of sequential bytes is of sufficient length to provide instruction data for at least two clock cycles.

摘要翻译： 描述了用于从指令数据的未分化字节序列中选择指令的方法和装置。 从指令数据的未分化字节的序列中选择指令数据的第一多个顺序字节。 从指令数据的第一多个顺序字节中选择从第一多个中的任何选定字节开始的指令数据的第二多个连续字节。 从指令数据的第二多个顺序字节中选择从第二多个中的任何选定字节开始的第三组连续字节的指令数据。 第二多个顺序字节具有足够的长度以提供至少两个时钟周期的指令数据。