公开(公告)号：US20070164787A1

公开(公告)日：2007-07-19

申请号：US11234548

申请日：2005-09-23

Applicant: Edward Grochowski ,  Chris Wilkerson ,  Shih-Lien Lu ,  Murali Annavaram

Inventor： Edward Grochowski ,  Chris Wilkerson ,  Shih-Lien Lu ,  Murali Annavaram

IPC: H03K19/173 ,  G06F7/38

CPC classification number: G01R31/31922 ,  G01R31/31726 ,  H03K5/1534 ,  H04L7/0083 ,  H04L7/033

Abstract: Two latches store the state of a data signal at a transition of a clock signal. Comparison logic compares the outputs of the two latches and produces a signal to indicate whether the outputs are equal or unequal. Systems using the latches and comparison logic are described and claimed.

Abstract translation: 两个锁存器在时钟信号的转变时存储数据信号的状态。 比较逻辑比较两个锁存器的输出，并产生一个信号以指示输出是相等还是不相等。 描述和要求保护使用锁存器和比较逻辑的系统。

公开(公告)号：US06938126B2

公开(公告)日：2005-08-30

申请号：US10121524

申请日：2002-04-12

Applicant: Alejandro Ramirez ,  Edward Grochowski ,  Hong Wang ,  John Shen

Inventor： Alejandro Ramirez ,  Edward Grochowski ,  Hong Wang ,  John Shen

IPC: G06F9/38 ,  G06F12/08 ,  G06F12/00

CPC classification number: G06F9/3814 ,  G06F9/3802 ,  G06F12/0882 ,  G06F12/0886 ,  Y02D10/13

Abstract: A method, apparatus, and system that compares a current fetch request having a first start address and length associated with the current fetch request to a second start address of the next fetch request, determines whether the content already loaded in a buffer will be used to at least partially fulfill the next fetch request based upon the comparison, and inhibits access to an instruction cache based upon the comparison.

Abstract translation: 将具有第一起始地址和与当前取出请求相关联的长度的当前提取请求与下一个提取请求的第二起始地址进行比较的方法，装置和系统确定已经加载在缓冲器中的内容是否将被用于 至少部分地基于比较来完成下一个提取请求，并且基于比较来禁止对指令高速缓存的访问。

公开(公告)号：US06904502B2

公开(公告)日：2005-06-07

申请号：US10743069

申请日：2003-12-23

Applicant: Nhon Quach ,  John Crawford ,  Greg S. Mathews ,  Edward Grochowski ,  Chakravarthy Kosaraju

Inventor： Nhon Quach ,  John Crawford ,  Greg S. Mathews ,  Edward Grochowski ,  Chakravarthy Kosaraju

IPC: G06F12/08 ,  G06F12/10 ,  G06F12/16 ,  G11C7/24

CPC classification number: G06F12/0891

Abstract: The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs using a blind invalidate circuit in high-speed memories. In accordance with an embodiment of the present invention, a tag array memory circuit including a plurality of memory bit circuits coupled together to form an n-bit memory cell; and a blind invalidate circuit coupled to a memory bit circuit in the n-bit memory cell, the blind invalidate circuit to clear a bit in the memory bit circuit, if a primary clear bit line is asserted and a received bit value of a right-adjacent memory bit circuit is zero.

Abstract translation: 本发明涉及高可靠性高性能微处理器的设计，更具体地涉及在高速存储器中使用盲目无效电路的设计。 根据本发明的实施例，一种标签阵列存储电路，包括耦合在一起以形成n位存储单元的多个存储器位电路; 以及与n位存储器单元中的存储器位电路耦合的盲目无效电路，盲目无效电路清除存储器位电路中的一位，如果主清零位线被断言，并且接收到的位值为右， 相邻的存储器位电路为零。

公开(公告)号：US06813628B2

公开(公告)日：2004-11-02

申请号：US09746771

申请日：2000-12-22

Applicant: Bharat Bhushan ,  Edward Grochowski ,  Vinod Sharma ,  John Crawford

Inventor： Bharat Bhushan ,  Edward Grochowski ,  Vinod Sharma ,  John Crawford

IPC: G06F704

CPC classification number: G06F7/5095 ,  G06F7/02 ,  G06F7/026 ,  G06F7/48 ,  G06F7/4824

Abstract: A method and apparatus is disclosed to compare numbers for equality. The numbers represented in a redundant form, including numbers received from a bypass circuit are subtracted. More specifically, a complemented form is generated and supplied to an arithmetic circuit for at least one number represented in the redundant form. Input to the arithmetic circuit is adjusted to augment a result generated through the arithmetic circuit to generate a valid outcome represented in the redundant form as a result of a subtraction operation. Results of the subtraction operation are compared to zero in redundant form using a non-propagative circuit and without requiring carry propagation, thereby producing an equality comparison of the number in redundant form.

Abstract translation: 公开了一种方法和装置，用于比较相等的数字。 减去以冗余形式表示的数字，包括从旁路电路接收的数字。更具体地，产生补码形式并将其提供给用冗余形式表示的至少一个数字的运算电路。 调整运算电路的输入以增加通过算术电路产生的结果，以产生作为减法运算的结果以冗余形式表示的有效结果。 使用非传播电路将减法操作的结果与冗余形式进行比较，而不需要进位传播，从而产生冗余形式的数量的等式比较。

公开(公告)号：US06775746B2

公开(公告)日：2004-08-10

申请号：US10435386

申请日：2003-05-12

Applicant: Nhon Quach ,  John Crawford ,  Greg S. Mathews ,  Edward Grochowski ,  Chakravarthy Kosaraju

Inventor： Nhon Quach ,  John Crawford ,  Greg S. Mathews ,  Edward Grochowski ,  Chakravarthy Kosaraju

IPC: G06F1210

CPC classification number: G06F12/0891

Abstract: The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs that use cache memory protection schemes such as, for example, a 1-hot plus valid bit scheme and a 2-hot vector cache scheme. These protection schemes protect the 1-hot vectors used in the tag array in the cache and are designed to provide hardware savings, operate at higher speeds and be simple to implement. In accordance with an embodiment of the present invention, a tag array memory circuit includes a plurality of memory bit circuits coupled together to form an n-bit memory cell, and a valid bit circuit coupled to the n-bit memory cell, the valid bit circuit being configured to be accessed simultaneously with the plurality of memory bit circuits.

公开(公告)号：US20170199825A1

公开(公告)日：2017-07-13

申请号：US15384054

申请日：2016-12-19

Applicant: Edward Grochowski ,  Julio Gago ,  Roger Gramunt ,  Roger Espasa ,  Rolf Kassa

Inventor： Edward Grochowski ,  Julio Gago ,  Roger Gramunt ,  Roger Espasa ,  Rolf Kassa

IPC: G06F12/1009 ,  G06F12/14 ,  G06F12/0864 ,  G06F12/1027

CPC classification number: G06F12/1009 ,  G06F12/0864 ,  G06F12/1027 ,  G06F12/145 ,  G06F2212/152 ,  G06F2212/6032 ,  G06F2212/652 ,  G06F2212/657 ,  G06F2212/68

Abstract: A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.

公开(公告)号：US20130219399A1

公开(公告)日：2013-08-22

申请号：US13843164

申请日：2013-03-15

Applicant: Hong Wang ,  John Shen ,  Edward Grochowski ,  Richard Hankins ,  Gautham Chinya ,  Bryant Bigbee ,  Shivnandan Kaushik ,  Xiang Chris Zou ,  Per Hammarlund ,  Scott Dion Rodgers ,  Xinmin Tian ,  Anil Aggawal ,  Prashant Sethi ,  Baiju Patel ,  James Held

Inventor： Hong Wang ,  John Shen ,  Edward Grochowski ,  Richard Hankins ,  Gautham Chinya ,  Bryant Bigbee ,  Shivnandan Kaushik ,  Xiang Chris Zou ,  Per Hammarlund ,  Scott Dion Rodgers ,  Xinmin Tian ,  Anil Aggawal ,  Prashant Sethi ,  Baiju Patel ,  James Held

IPC: G06F9/48

CPC classification number: G06F9/3867 ,  G06F9/30003 ,  G06F9/30043 ,  G06F9/3005 ,  G06F9/3009 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/3851 ,  G06F9/4843 ,  G06F9/4881

Abstract: In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.

Abstract translation: 在一个实施例中，提供了一种方法。 该方法包括响应于在应用级程序的控制下对第二指令定序器执行用户级指令来管理第一指令定序器上的用户级线程。 在第二指令定序器上运行第一用户级线程并且包含一个或多个用户级指令。 第一用户级指令至少具有1）引用一个或多个指令定序器的字段，或者2）使用指向代码执行代码时特定寻址一个或多个指令定序器的代码的指针进行隐式引用。

公开(公告)号：US20110154000A1

公开(公告)日：2011-06-23

申请号：US12653800

申请日：2009-12-18

Applicant: Joshua B. Fryman ,  Andrew Thomas Forsyth ,  Edward Grochowski

Inventor： Joshua B. Fryman ,  Andrew Thomas Forsyth ,  Edward Grochowski

IPC: G06F9/30 ,  G06F12/08

CPC classification number: G06F9/3004 ,  G06F9/30087

Abstract: A technique to perform a fast compare-exchange operation is disclosed. More specifically, a machine-readable medium, processor, and system are described that implement a fast compare-exchange operation as well as a cache line mark operation that enables the fast compare-exchange operation.

Abstract translation: 公开了一种执行快速比较交换操作的技术。 更具体地，描述了实现快速比较交换操作以及启用快速比较交换操作的高速缓存行标记操作的机器可读介质，处理器和系统。

公开(公告)号：US07395304B2

公开(公告)日：2008-07-01

申请号：US10890848

申请日：2004-07-13

Applicant: Bharat Bhushan ,  Vinod Sharma ,  Edward Grochowski ,  John Crawford

Inventor： Bharat Bhushan ,  Vinod Sharma ,  Edward Grochowski ,  John Crawford

IPC: G06F7/04

CPC classification number: G06F7/5095 ,  G06F7/02 ,  G06F7/4824

Abstract: A method and apparatus is disclosed that uses an arithmetic circuit for adding numbers represented in a redundant form to also subtract numbers received in redundant form, including numbers received from a bypass circuit. A non-propagative comparator circuit is then used to compare a given value with a result from the arithmetic circuit to determine if the result is equal to the given value. All of the operations described above can be accomplished without propagating carry signals throughout the circuitry.The method includes generating a complemented redundant form of at least one number supplied to the arithmetic circuit in redundant form. It also includes providing adjustment input to the arithmetic circuit to augment a result produced through the arithmetic circuit. This adjustment causes the arithmetic circuit to generate a valid outcome in redundant form as a result of a subtraction operation if the arithmetic operation is subtraction. Then the result is compared to a given value using a non-propagative comparator to determine equality or inequality of the result to the given value.

Abstract translation: 公开了一种方法和装置，其使用运算电路来添加以冗余形式表示的数字，还可以减去以冗余形式接收的数字，包括从旁路电路接收的数字。 然后使用非传播比较器电路将给定值与运算电路的结果进行比较，以确定结果是否等于给定值。 可以在整个电路中不传播进位信号来实现上述所有操作。 该方法包括以冗余的形式生成提供给运算电路的至少一个数的补码冗余形式。 它还包括向算术电路提供调整输入以增加通过运算电路产生的结果。 如果算术运算是减法，则该调整使得运算电路作为减法运算的结果以冗余形式产生有效结果。 然后将结果与使用非传播比较器的给定值进行比较，以确定结果与给定值的相等或不等式。

公开(公告)号：US06954848B2

公开(公告)日：2005-10-11

申请号：US10038038

申请日：2002-01-02

Applicant: Ryan Rakvic ,  Christopher Wilkerson ,  Bryan Black ,  Edward Grochowski ,  John Shen ,  Edward Brekelbaum

Inventor： Ryan Rakvic ,  Christopher Wilkerson ,  Bryan Black ,  Edward Grochowski ,  John Shen ,  Edward Brekelbaum

IPC: G06F9/00 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3824 ,  G06F9/3836 ,  G06F9/3838

Abstract: After an instruction loads data into a register at a first time, the register is monitored to see if it is read in a next clock cycle. When the data is not read in the next clock cycle, the instruction is classified as a slowable instruction. An instruction address associated with the instruction is used to update a history table. The history table stores information to indicate if an instruction is a slowable instruction or a non-slowable instruction. When the instruction address of the instruction is encountered at a second time, the history table is used to determine if the instruction is slowable or non-slowable.

Abstract translation: 在第一次指令将数据加载到寄存器中之后，监视寄存器以查看是否在下一个时钟周期读取。 当数据在下一个时钟周期内未被读取时，指令被分类为慢指令。 与指令相关联的指令地址用于更新历史表。 历史表存储用于指示指令是指令是慢指令还是非慢指令的信息。 当第二次遇到指令的指令地址时，使用历史表来确定指令是可慢还是不慢。