Ferroelectric memory configuration having successively connected ferroelectric capacitor coupling to the gate of a read transistor and different bias voltages applied in read/write/erase
    11.
    发明授权
    Ferroelectric memory configuration having successively connected ferroelectric capacitor coupling to the gate of a read transistor and different bias voltages applied in read/write/erase 失效
    铁电存储器配置具有连续的铁电电容器耦合到读取晶体管的栅极和在读/写/擦除中施加的不同偏置电压

    公开(公告)号:US06967859B2

    公开(公告)日:2005-11-22

    申请号:US10626722

    申请日:2003-07-25

    IPC分类号: G11C11/22

    CPC分类号: G11C11/22 G11C11/223

    摘要: A semiconductor memory of this invention contains a memory cell block including a plurality of ferroelectric capacitors successively connected to one another along a bit line direction each for storing a data in accordance with displacement of polarization of a ferroelectric film thereof, and a reading transistor whose gate is connected to one end of the successively connected plural ferroelectric capacitors for reading a data by detecting the displacement of the polarization of the ferroelectric film of a ferroelectric capacitor selected from the plural ferroelectric capacitors. A set line is connected to the other end of the successively connected plural ferroelectric capacitors. A bit line is connected to the drain of the reading transistor at one end thereof. A reset line is connected to the source of the reading transistor at one end thereof. A plurality of word lines respectively corresponding to the plural ferroelectric capacitors are provided perpendicularly to the bit line, so as to select a ferroelectric capacitor from the plural ferroelectric capacitors for data write or data read.

    摘要翻译: 本发明的半导体存储器包括存储单元块,该存储单元块包括沿着位线方向依次连接的多个强电介质电容器,每个强电介质电容器用于根据其铁电体膜的极化位移存储数据;以及读取晶体管,其栅极 通过检测从多个强电介质电容器中选出的铁电体电容器的铁电体膜的极化位移来连接到连续连接的多个铁电电容器的一端,用于读取数据。 设定线连接到连续连接的多个铁电电容器的另一端。 位线在其一端连接到读取晶体管的漏极。 复位线在其一端连接到读取晶体管的源极。 分别对应于多个强电介质电容器的多个字线垂直于位线设置,以从多个用于数据写入或数据读取的强电介质电容器中选择铁电电容器。

    Non-volatile semiconductor memory device with enhanced erase/write cycle endurance
    13.
    发明授权
    Non-volatile semiconductor memory device with enhanced erase/write cycle endurance 失效
    具有增强的擦除/写入周期耐久性的非易失性半导体存储器件

    公开(公告)号:US06693840B2

    公开(公告)日:2004-02-17

    申请号:US10271139

    申请日:2002-10-15

    IPC分类号: G11C700

    CPC分类号: G11C14/00 G11C16/30

    摘要: The power-supply unit, while directing externally supplied power to the control unit and the like, accumulates an amount of power that is required by the control unit to save data from the volatile memory to the non-volatile memory. When an external power supply has started, the control unit restores data of the non-volatile memory in the volatile memory; and when the external power supply has stopped, the control unit saves data from the volatile memory to the non-volatile memory.

    摘要翻译: 电源单元在向控制单元等引导外部供电的同时,累积控制单元所需的功率量,以将数据从易失性存储器保存到非易失性存储器。 当外部电源开始时,控制单元恢复易失性存储器中的非易失性存储器的数据; 并且当外部电源停止时,控制单元将数据从易失性存储器保存到非易失性存储器。

    Semiconductor memory device having MFMIS transistor and increased data storage time
    14.
    发明授权
    Semiconductor memory device having MFMIS transistor and increased data storage time 失效
    具有MFMIS晶体管的半导体存储器件和增加的数据存储时间

    公开(公告)号:US06509594B2

    公开(公告)日:2003-01-21

    申请号:US09874319

    申请日:2001-06-06

    IPC分类号: H01L31062

    摘要: The semiconductor memory of this invention includes an MFMIS transistor including a field effect transistor and a ferroelectric capacitor formed above the field effect transistor. The semiconductor memory has a characteristic that a value of (&sgr;−p) is substantially not changed with time in a relational expression, V=(d/&egr;0)×(&sgr;−p), which holds among a potential difference V between an upper electrode and a lower electrode, a surface density of charge &sgr; of a ferroelectric film, polarization charge p of the ferroelectric film, a thickness d of the ferroelectric film and a dielectric constant &egr;0 of vacuum when a data is written in the MFMIS transistor and the ferroelectric film is in a polarized state.

    摘要翻译: 本发明的半导体存储器包括一个包括场效应晶体管和形成在场效应晶体管之上的铁电电容器的MFMIS晶体管。 半导体存储器具有以下关系式中的时间(sigma-p)基本上不随时间变化的特性,V =(d / epsi0)x(sigma-p)),其保持在上 电极和下电极,强电介质膜的电荷sigma的表面密度,铁电体膜的极化电荷p,强电介质膜的厚度d和当数据被写入MFMIS晶体管时的真空的介电常数εi0,以及 铁电薄膜处于极化状态。

    Method for driving semiconductor memory
    15.
    发明授权
    Method for driving semiconductor memory 失效
    驱动半导体存储器的方法

    公开(公告)号:US06449184B2

    公开(公告)日:2002-09-10

    申请号:US09879079

    申请日:2001-06-13

    IPC分类号: G11C1122

    CPC分类号: G11C11/22 G11C11/223

    摘要: In a method for driving a semiconductor memory including a ferroelectric capacitor for storing a multi-valued data in accordance with a displacement of polarization of a ferroelectric film and a detector connected to one of an upper electrode and a lower electrode of the ferroelectric capacitor for detecting the displacement of the polarization of the ferroelectric film, the multi-valued data is read by detecting the displacement of the polarization of the ferroelectric film by the detector under application of a reading voltage to the other of the upper electrode and the lower electrode of the ferroelectric capacitor, and then, the reading voltage applied to the latter electrode is removed. The reading voltage has such magnitude that the displacement of the polarization of the ferroelectric film is restored to that obtained before reading the multi-valued data by removing the reading voltage.

    摘要翻译: 一种用于驱动半导体存储器的方法,所述半导体存储器包括:强电介质电容器,用于根据强电介质膜的极化位移存储多值数据;以及检测器,连接到用于检测的铁电电容器的上电极和下电极之一 通过在施加读取电压的情况下检测由检测器对强电介质膜的极化的位移,读取多层数据的多值数据, 铁电电容器,然后,去除施加到后一电极的读取电压。 读取电压具有这样的大小,使得铁电薄膜的偏振的位移恢复到通过去除读取电压读取多值数据之前获得的位移。

    Semiconductor memory device and drive method therefor
    16.
    发明授权
    Semiconductor memory device and drive method therefor 失效
    半导体存储器件及其驱动方法

    公开(公告)号:US06707704B2

    公开(公告)日:2004-03-16

    申请号:US10392843

    申请日:2003-03-21

    IPC分类号: G11C1122

    CPC分类号: G11C11/22

    摘要: The semiconductor memory device of the invention includes at least three memory cell blocks arranged in a word line direction. Each of the memory cell blocks includes a plurality of memory cells arranged in a bit line direction. Each of the memory cells includes a ferroelectric capacitor for storing data by displacement of polarization of a ferroelectric film and a selection transistor connected to one of paired electrodes of the ferroelectric capacitor. Each of the memory cell blocks also includes: a bit line, a sub-bit line and a source line extending in the bit line direction; and a read transistor having a gate connected to one end of the sub-bit line, a source connected to the source line, and a drain connected to one end of the bit line. The read transistor reads data by detecting the displacement of the polarization of the ferroelectric film of the ferroelectric capacitor of a data read memory cell from which data is read among the plurality of memory cells. The sub-bit lines of any two of the memory cell blocks are connected to each other via a sub-bit line coupling switch.

    摘要翻译: 本发明的半导体存储器件包括沿字线方向布置的至少三个存储单元块。 每个存储单元块包括以位线方向排列的多个存储单元。 每个存储单元包括用于通过铁电薄膜的极化位移存储数据的铁电电容器和连接到铁电体电容器的一对电极之一的选择晶体管。 每个存储单元块还包括:位线,子位线和沿位线方向延伸的源极线; 以及读取晶体管,其具有连接到子位线的一端的栅极,连接到源极线的源极和连接到位线的一端的漏极。 读取晶体管通过检测在多个存储单元中从其读取数据的数据读取存储单元的铁电电容器的铁电体的极化的位移来读取数据。 任何两个存储单元块的子位线通过子位线耦合开关相互连接。

    Semiconductor device
    17.
    发明申请
    Semiconductor device 审中-公开
    半导体器件

    公开(公告)号:US20060095975A1

    公开(公告)日:2006-05-04

    申请号:US11212585

    申请日:2005-08-29

    IPC分类号: H04L9/32

    CPC分类号: G06F21/79 H04L9/085

    摘要: A semiconductor device of the present invention includes: at least one of non-volatile memory unit operable to store data; at least one of an arithmetic-logic unit operable to perform an arithmetic-logic operation using data which is stored in the memory unit and data that is inputted from outside; and an output unit operable to output a result of arithmetic-logic operation performed by the arithmetic-logic unit; wherein the memory unit, the arithmetic-logic unit, and the output unit are included in a functional block, and an output line of each of the memory unit is connected only to one of at least one of the arithmetic-logic unit.

    摘要翻译: 本发明的半导体器件包括:用于存储数据的非易失性存储单元中的至少一个; 算术逻辑单元中的至少一个,其可操作以使用存储在存储单元中的数据和从外部输入的数据执行算术运算; 以及输出单元,其可操作以输出由所述算术单元执行的算术逻辑运算的结果; 其中所述存储器单元,所述算术逻辑单元和所述输出单元包括在功能块中,并且所述存储器单元中的每一个的输出线仅与所述算术单元中的至少一个连接。

    Ferroelectric memory and method of operating same
    18.
    发明授权
    Ferroelectric memory and method of operating same 有权
    铁电存储器和操作方法相同

    公开(公告)号:US06924997B2

    公开(公告)日:2005-08-02

    申请号:US10381235

    申请日:2001-09-25

    IPC分类号: G11C11/22

    CPC分类号: G11C11/22

    摘要: A ferroelectric memory 636 includes a group of memory cells (645, 12, 201, 301, 401, 501), each cell having a ferroelectric memory element (44, 218, etc.), a drive line (122, 322, 422, 522 etc.) on which a voltage for writing information to the group of memory cells is placed, a bit line (25, 49, 125, 325, 425, 525, etc.) on which information to be read out of the group of memory cells is placed, a preamplifier (20, 42, 120, 320, 420, etc.) between the memory cells and the bit line, a set switch (14, 114, 314, 414, 514, etc.) connected between the drive line and the memory cells, and a reset switch (16, 116, 316, 416, 516, etc.) connected to the memory cells in parallel with the preamplifier. The memory is read by placing a voltage less than the coercive voltage of the ferroelectric memory element across a memory element. Prior to reading, noise from the group of cells is discharged by grounding both electrodes of the ferroelectric memory element.

    摘要翻译: 铁电存储器636包括一组存储单元(645,12,21,301,401,501),每个单元具有铁电存储元件(44,218等),驱动线(122,322,422, 522等),在其上放置用于将信息写入到存储器单元组的电压,位线(25,49,125,325,425,525等),其中要从该组存储器单元读出的信息 放置存储器单元,在存储器单元和位线之间的前置放大器(20,42,120,320,420等),连接在存储器单元之间的设定开关(14,114,314,414,514等) 驱动线和存储器单元,以及与前置放大器并联连接到存储器单元的复位开关(16,116,316,416,516等)。 通过将小于铁电存储元件的矫顽电压的电压放置在存储元件上来读取存储器。 在读取之前,通过使铁电存储元件的两个电极接地来放电来自该组电池的噪声。

    Semiconductor memory and method for driving the same

    公开(公告)号:US06614678B2

    公开(公告)日:2003-09-02

    申请号:US09905893

    申请日:2001-07-17

    IPC分类号: G11C1122

    CPC分类号: G11C11/22 G11C11/223

    摘要: A semiconductor memory of this invention contains a memory cell block including a plurality of ferroelectric capacitors successively connected to one another along a bit line direction each for storing a data in accordance with displacement of polarization of a ferroelectric film thereof, and a reading transistor whose gate is connected to one end of the successively connected plural ferroelectric capacitors for reading a data by detecting the displacement of the polarization of the ferroelectric film of a ferroelectric capacitor selected from the plural ferroelectric capacitors. A set line is connected to the other end of the successively connected plural ferroelectric capacitors. A bit line is connected to the drain of the reading transistor at one end thereof. A reset line is connected to the source of the reading transistor at one end thereof. A plurality of word lines respectively corresponding to the plural ferroelectric capacitors are provided perpendicularly to the bit line, so as to select a ferroelectric capacitor from the plural ferroelectric capacitors for data write or data read.

    Semiconductor memory and method for driving the same
    20.
    发明授权
    Semiconductor memory and method for driving the same 失效
    半导体存储器及其驱动方法

    公开(公告)号:US06456520B1

    公开(公告)日:2002-09-24

    申请号:US09941736

    申请日:2001-08-30

    IPC分类号: G11C1122

    CPC分类号: G11C11/22

    摘要: The semiconductor memory of this invention includes a plurality of ferroelectric capacitors successively connected to one another in a bit line direction each for storing a data in accordance with displacement of polarization of a ferroelectric film thereof; a plurality of selecting transistors respectively connected to the plurality of ferroelectric capacitor in parallel for selecting a selected ferroelectric capacitor from the plural ferroelectric capacitors; a set line connected to a first end of a series circuit including the plural successively connected ferroelectric capacitors to which a reading voltage is applied; and a load capacitor connected to a second end of the series circuit for detecting displacement of polarization of the ferroelectric film of the selected ferroelectric capacitor. In the series circuit, capacitance is larger in a ferroelectric capacitor disposed in a position relatively near to the first end of the series circuit than in a ferroelectric capacitor disposed in a position relatively far from the first end.

    摘要翻译: 本发明的半导体存储器包括在位线方向上相继连接的多个铁电电容器,用于根据其铁电体膜的极化位移来存储数据; 分别与所述多个铁电电容器并联连接的多个选择晶体管,用于从所述多个铁电电容器中选择所选择的铁电电容器; 连接到串联电路的第一端的设定线,该串联电路包括多个依次连接的强电介质电容器,其中施加了读取电压; 连接到串联电路的第二端的负载电容器,用于检测所选铁电电容器的铁电体膜的极化位移。 在串联电路中,布置在比串联电路的第一端更靠近串联电路的第一端的铁电电容器中的电容大于布置在距第一端相对较远的位置的铁电电容器中的电容。