公开(公告)号：US07593291B2

公开(公告)日：2009-09-22

申请号：US10926227

申请日：2004-08-26

申请人： Tomohiko Ito

发明人： Tomohiko Ito

IPC分类号： G04B47/00 ,  G03G21/14 ,  G05D17/00

CPC分类号： G04G15/006

摘要： Based on regional calendar data including weekday information and holiday information, days of a month to be set are displayed as date buttons in a nonconsultation day setting image. A WORK button, an ALL button, a PM button or an AM button may be clicked to set consultation days and nonconsultation days for each day or weekday. The amount of energy consumed by an image forming apparatus is reduced by an energy saving mode in a preset nonbusiness time zone on nonbusiness days, and on Sundays and holidays which are not working days.

摘要翻译： 根据包括工作日信息和假日信息在内的区域日历数据，在非咨询日设置图像中显示要设置的一天的日期作为日期按钮。 可以单击“工作”按钮，全部按钮，PM按钮或AM按钮，以设置每天或工作日的咨询日期和非参考日期。 图像形成装置消耗的能量的量在非工作日的预设非商业时区的节能模式以及不工作日的星期日和假日减少。

公开(公告)号：US20090184857A1

公开(公告)日：2009-07-23

申请号：US12349180

申请日：2009-01-06

申请人： Masanori Furuta ,  Tomohiko Ito ,  Takafumi Yamaji ,  Tetsuro Itakura

发明人： Masanori Furuta ,  Tomohiko Ito ,  Takafumi Yamaji ,  Tetsuro Itakura

IPC分类号： H03M1/12

CPC分类号： H03M1/1215 ,  H03M1/162 ,  H03M1/164 ,  H03M1/468

摘要： An A/D converting apparatus includes a first A/D converter to sample an analog input signal having a D/A converter to generate a comparative signal for successive comparison with the analog input signal, a signal generator generate a differential signal between the analog input signal and the comparative signal, and a comparator to compare the comparative signal with a standard value to generate a first digital signal exhibiting high-order bit; an amplifier to amplify the differential signal to generate a residue signal; and a second A/D converter to sample the residue signal to generate a second digital signal exhibiting low-order bit.

摘要翻译： A / D转换装置包括：第一A / D转换器，对具有D / A转换器的模拟输入信号进行采样以产生用于与模拟输入信号连续比较的比较信号，信号发生器在模拟输入端之间产生差分信号 信号和比较信号，以及比较器，用于将比较信号与标准值进行比较，以产生呈现高位的第一数字信号; 放大器，用于放大差分信号以产生残留信号; 以及第二A / D转换器，用于对残留信号进行采样以产生呈现低阶位的第二数字信号。

公开(公告)号：US20070210869A1

公开(公告)日：2007-09-13

申请号：US11618071

申请日：2006-12-29

申请人： Tomohiko Ito ,  Tetsuro Itakura

发明人： Tomohiko Ito ,  Tetsuro Itakura

IPC分类号： H03F3/45

CPC分类号： H03F3/45179

摘要： Disclosed is a differential amplifying circuit including an amplifying circuit, wherein 1) a drain of a sixth transistor is connected to a drain of an eighth transistor, and a drain of a tenth transistor is connected to a drain of a fourth transistor, and 2) a ratio between a total of gate widths of the fourth (or eighth) and tenth (or sixth) transistors (converted per unit gate length, and gate widths that follow are the same)and a gate width of a fifth (or ninth) transistor is nearly proportional to a current ratio between a first (or third) and second (or fourth) current source circuits, the gate width of the fourth (or eighth) transistor being equal to or more than that of the tenth (or sixth) transistor.

摘要翻译： 公开了一种包括放大电路的差分放大电路，其中1）第六晶体管的漏极连接到第八晶体管的漏极，第十晶体管的漏极连接到第四晶体管的漏极，以及2） 第四（或第八）和第十（或第六）晶体管（每单位栅极长度转换，并且随后的栅极宽度相同）的栅极宽度的总和与第五（或第九）晶体管 与第一（或第三）和第二（或第四）电流源电路之间的电流比几乎成比例，第四（或第八）晶体管的栅极宽度等于或大于第十（或第六）晶体管的栅极宽度 。

公开(公告)号：US20050047279A1

公开(公告)日：2005-03-03

申请号：US10926227

申请日：2004-08-26

申请人： Tomohiko Ito

发明人： Tomohiko Ito

IPC分类号： B41J29/38 ,  G03G21/00 ,  G04G15/00 ,  G06F3/12 ,  H04N1/00 ,  G04F8/00 ,  G04B47/00

CPC分类号： G04G15/006

摘要： Based on regional calendar data including weekday information and holiday information, days of a month to be set are displayed as date buttons in a nonconsultation day setting image. A WORK button, an ALL button, a PM button or an AM button may be clicked to set consultation days and nonconsultation days for each day or weekday. The amount of energy consumed by an image forming apparatus is reduced by an energy saving mode in a preset nonbusiness time zone on nonbusiness days, and on Sundays and holidays which are not working days.

摘要翻译： 根据包括工作日信息和假日信息在内的区域日历数据，在非咨询日设置图像中显示要设置的日期，作为日期按钮。 可以单击“工作”按钮，全部按钮，PM按钮或AM按钮，以设置每天或工作日的咨询日期和非参考日期。 图像形成装置消耗的能量的量在非工作日的预设非商业时区的节能模式以及不工作日的星期日和假日减少。

公开(公告)号：US07868797B2

公开(公告)日：2011-01-11

申请号：US12469736

申请日：2009-05-21

申请人： Tomohiko Ito

发明人： Tomohiko Ito

IPC分类号： H03M1/00

CPC分类号： H03F3/45475 ,  G11C27/026 ,  H03F2203/45134 ,  H03F2203/45136 ,  H03F2203/45514 ,  H03F2203/45551

摘要： There is disclosed a sample-and-hold circuit. An operational amplifier includes an inverting input terminal, a non-inverting input terminal, an inverting output terminal, and a non-inverting output terminal. First and second groups of capacitors are operated in first to third modes periodically. Positive and negative input signals are input to charge an electric charge in the first mode, electric charge are held while positive and negative output signals are output from the operational amplifier by connecting between the inverting input terminal and the non-inverting output terminal and by connecting between the non-inverting input terminal and the inverting output terminal in the second mode, and electric charge are discharged in the third mode. Second group of capacitors shifts to the third mode when first group of capacitors is in the first or second mode, and shift to the first or second mode when first group of capacitors is in the third mode.

摘要翻译： 公开了采样保持电路。 运算放大器包括反相输入端子，非反相输入端子，反相输出端子和非反相输出端子。 第一组和第二组电容器周期性地以第一至第三模式工作。 输入正负输入信号以在第一模式下对电荷充电，保持电荷，同时通过连接反相输入端和非反相输出端从运算放大器输出正和负输出信号，并通过连接 在第二模式中的非反相输入端子和反相输出端子之间，并且在第三模式中电荷被放电。 当第一组电容器处于第一或第二模式时，第二组电容器移动到第三模式，并且当第一组电容器处于第三模式时，转换到第一或第二模式。

公开(公告)号：US07532069B2

公开(公告)日：2009-05-12

申请号：US12173431

申请日：2008-07-15

申请人： Tomohiko Ito ,  Tetsuro Itakura

发明人： Tomohiko Ito ,  Tetsuro Itakura

IPC分类号： H03F3/45

CPC分类号： H03F3/45179

摘要： Disclosed is a differential amplifying circuit including an amplifying circuit, wherein 1) a drain of a sixth transistor is connected to a drain of an eighth transistor, and a drain of a tenth transistor is connected to a drain of a fourth transistor, and 2) a ratio between a total of gate widths of the fourth (or eighth) and tenth (or sixth) transistors (converted per unit gate length, and gate widths that follow are the same) and a gate width of a fifth (or ninth) transistor is nearly proportional to a current ratio between a first (or third) and second (or fourth) current source circuits, the gate width of the fourth (or eighth) transistor being equal to or more than that of the tenth (or sixth) transistor.

摘要翻译： 公开了一种包括放大电路的差分放大电路，其中1）第六晶体管的漏极连接到第八晶体管的漏极，第十晶体管的漏极连接到第四晶体管的漏极，以及2） 第四（或第八）和第十（或第六）晶体管（每单位栅极长度转换，并且随后的栅极宽度相同）的栅极宽度的总和与第五（或第九）晶体管 几乎与第一（或第三）和第二（或第四）电流源电路之间的电流比成比例，第四（或第八）晶体管的栅极宽度等于或大于第十（或第六）晶体管的栅极宽度 。

公开(公告)号：US07414472B2

公开(公告)日：2008-08-19

申请号：US11618071

申请日：2006-12-29

申请人： Tomohiko Ito ,  Tetsuro Itakura

发明人： Tomohiko Ito ,  Tetsuro Itakura

IPC分类号： H03F3/45

CPC分类号： H03F3/45179

摘要： Disclosed is a differential amplifying circuit including an amplifying circuit, wherein 1) a drain of a sixth transistor is connected to a drain of an eighth transistor, and a drain of a tenth transistor is connected to a drain of a fourth transistor, and 2) a ratio between a total of gate widths of the fourth (or eighth) and tenth (or sixth) transistors (converted per unit gate length, and gate widths that follow are the same)and a gate width of a fifth (or ninth) transistor is nearly proportional to a current ratio between a first (or third) and second (or fourth) current source circuits, the gate width of the fourth (or eighth) transistor being equal to or more than that of the tenth (or sixth) transistor.

摘要翻译： 公开了一种包括放大电路的差分放大电路，其中1）第六晶体管的漏极连接到第八晶体管的漏极，第十晶体管的漏极连接到第四晶体管的漏极，以及2） 第四（或第八）和第十（或第六）晶体管（每单位栅极长度转换，并且随后的栅极宽度相同）的栅极宽度的总和与第五（或第九）晶体管 与第一（或第三）和第二（或第四）电流源电路之间的电流比几乎成比例，第四（或第八）晶体管的栅极宽度等于或大于第十（或第六）晶体管的栅极宽度 。

公开(公告)号：US07276007B2

公开(公告)日：2007-10-02

申请号：US11089204

申请日：2005-03-25

申请人： Shigeki Takami ,  Kozo Yamaguchi ,  Takeshi Inuzuka ,  Tomohiko Ito

发明人： Shigeki Takami ,  Kozo Yamaguchi ,  Takeshi Inuzuka ,  Tomohiko Ito

IPC分类号： F16H3/72

CPC分类号： B60K6/365 ,  B60K1/02 ,  B60K6/387 ,  B60K6/445 ,  B60W10/10 ,  F16H3/728 ,  F16H2037/0866 ,  F16H2037/104 ,  F16H2200/2007 ,  Y02T10/6239

摘要： A hybrid drive unit includes a three-element planetary gear coupled to two motors, and a reduction planetary gear which is drivingly connected to the three-element planetary gear and switches modes by controlling a clutch and a brake. A three-element direct drive mode is able to be achieved by providing another clutch which couples together any two elements of the reduction planetary gear, and locking up the reduction planetary gear. As a result, motor output is reduced compared with a four-element direct drive mode of related art during high-speed running, and energy recovery efficiency during regeneration can also be improved.

摘要翻译： 混合驱动单元包括联接到两个电动机的三元件行星齿轮和通过控制离合器和制动器驱动地连接到三元件行星齿轮并切换模式的减速行星齿轮。 通过提供将还原行星齿轮的任何两个元件连接在一起的另一个离合器并且锁定还原行星齿轮，能够实现三元件直接驱动模式。 结果，与高速行驶中的相关技术的四元件直接驱动模式相比，电动机输出减少，并且还可以提高再生时的能量回收效率。

公开(公告)号：US06873351B2

公开(公告)日：2005-03-29

申请号：US10396413

申请日：2003-03-26

申请人： Tomohiko Ito

发明人： Tomohiko Ito

IPC分类号： G03B27/72 ,  G03C1/498 ,  H04N1/32 ,  H04N1/60 ,  B41J2/435 ,  G06K1/00

CPC分类号： H04N1/6097 ,  H04N1/32122 ,  H04N1/603 ,  H04N2201/3204 ,  H04N2201/3276

摘要： In a medical facility, image forming apparatus are connected to a local area network, and the characteristics of the photosensitive mediums are stored in a database connected to the local area network. When new photosensitive mediums are loaded in a certain image forming apparatus, attribute information of the new photosensitive mediums is transmitted to the database via the local area network. If the characteristics of the photosensitive mediums depending on the attribute information are stored in the database, then the characteristics of the photosensitive mediums are downloaded from the database via the local area network into the certain image forming apparatus. The characteristics of the photosensitive mediums can thus be shared among the image forming apparatus.

摘要翻译： 在医疗设施中，图像形成装置连接到局域网，并且感光介质的特性被存储在连接到局域网的数据库中。 当将新的感光介质装载在特定的图像形成装置中时，新的感光介质的属性信息经由局域网传送到数据库。 如果根据属性信息将感光介质的特性存储在数据库中，则将感光介质的特性从数据库经由局域网下载到特定的图像形成装置中。 因此，可以在图像形成装置之间共享光敏介质的特性。

公开(公告)号：US5844194A

公开(公告)日：1998-12-01

申请号：US668008

申请日：1996-06-19

申请人： Mitsuo Kuwabara ,  Kiyoshi Ikegami ,  Tomohiko Ito ,  Teruaki Yoshida

发明人： Mitsuo Kuwabara ,  Kiyoshi Ikegami ,  Tomohiko Ito ,  Teruaki Yoshida

IPC分类号： B22D23/00 ,  B22F7/08 ,  B23K11/18 ,  B23K11/30 ,  B23K35/02 ,  B23K35/04 ,  B23K35/40 ,  C22C47/00 ,  C22C47/02 ,  C22C47/14

CPC分类号： C22C47/025 ,  B22F7/08 ,  B23K35/0205 ,  B23K35/402 ,  C22C47/00 ,  C22C47/14 ,  B22F2998/00 ,  B23K11/30

摘要： A resistance welding electrode for supplying a current to metal workpieces to weld the workpieces to each other includes an electrode body as an electrode matrix of a copper alloy and a plurality of filamentary members embedded in the electrode matrix parallel to the direction in which a current flows therethrough. The filamentary members have respective tip ends exposed as lands on a surface of a tip end of the electrode body. The filamentary members are made of a material having an electric conductivity different from that of the electrode matrix. The exposed tip ends of the filamentary members having a total area which is in the range of 0.5 to 40% of the entire area of the tip end of the electrode body.

摘要翻译： 用于向金属工件供应电流以焊接工件的电阻焊接电极彼此包括作为铜合金的电极基体的电极体和与电流流动方向平行的电极基体中嵌入的多个丝状部件 通过。 丝状部件具有各自的末端作为焊盘暴露在电极体的前端的表面上。 丝状部件由具有不同于电极基体的电导率的材料制成。 丝状部件的露出端部的总面积在电极体的前端的整个面积的0.5〜40％的范围内。