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    Liquid crystal display module, using a flexible printed circuit board with enhanced thermocompression characteristics
    12.
    发明授权
    Liquid crystal display module, using a flexible printed circuit board with enhanced thermocompression characteristics 有权
    液晶显示模块，采用柔性印刷电路板，具有增强的热压特性

    公开(公告)号：US06519020B1

    公开(公告)日：2003-02-11

    申请号：US09357884

    申请日：1999-07-21

    申请人： Ki-Seok Cha ,  Myung-Chul Kim ,  Won-Seok Lee

    发明人： Ki-Seok Cha ,  Myung-Chul Kim ,  Won-Seok Lee

    IPC分类号： G02F11345

    CPC分类号： G02F1/13452 ,  H05K1/147

    摘要： An LCD module uses a flexible printed circuit (FPC) instead of a gate or a source drive printed circuit board (PCB) so that size of area by which a tape carrier package (TCP) is thermocompression molded can be substantially decreased and thus reducing a difference in the degree of thermal expansion between PCB and TCP. As a result, a slim and lightweight LCD module can be obtained, and a misalignment or a warpage of TCP can be prevented.

    摘要翻译： LCD模块使用柔性印刷电路（FPC）来代替栅极或源极驱动印刷电路板（PCB），从而能够大大减少带状载体封装（TCP）被热压成型的区域尺寸，从而减少 PCB和TCP之间的热膨胀程度的差异。 结果，可以获得纤细和轻便的LCD模块，并且可以防止TCP的未对准或翘曲。

    APPARATUS FOR GENERATING SECURE KEY USING DEVICE AND USER AUTHENTICATION INFORMATION
    14.
    发明申请
    APPARATUS FOR GENERATING SECURE KEY USING DEVICE AND USER AUTHENTICATION INFORMATION 有权
    用于使用设备产生安全密钥的设备和用户认证信息

    公开(公告)号：US20130318358A1

    公开(公告)日：2013-11-28

    申请号：US13798475

    申请日：2013-03-13

    申请人： Weixin Wang ,  Hee-Chang Cho ,  Won-Seok Lee ,  Min-Wook Kim ,  Hyoung-Suk Jang

    发明人： Weixin Wang ,  Hee-Chang Cho ,  Won-Seok Lee ,  Min-Wook Kim ,  Hyoung-Suk Jang

    IPC分类号： G06F21/31

    CPC分类号： G06F21/31 ,  G06F21/57 ,  G06F2221/2105 ,  G06F2221/2107 ,  H04L9/0866

    摘要： A secure key generating apparatus comprising an ID calculating unit receiving a primitive ID from a first storage device and calculating a first media ID, (a unique identifier of the first storage device), from the first primitive ID; a user authentication information providing unit providing user authentication information for authenticating the current; and a secure key generating unit for generating a first Secure Key using both the first media ID and the first user's authentication information. The Secure Key is used to encrypt/decrypt content stored in the first storage device. The secure key generating unit generates a first different Secure Key using a second media ID of a second storage device, and generates a second different Secure Key using second user's user authentication information. Only the first Secure Key can be used to decrypt encrypted content stored in the first storage device that was encrypted using the first Secure Key.

    摘要翻译： 一种安全密钥生成装置，包括ID计算单元，从第一存储装置接收原始ID，并从第一基元ID计算第一媒体ID（第一存储装置的唯一标识符）; 用户认证信息提供单元提供用于认证当前的用户认证信息; 以及安全密钥生成单元，用于使用第一媒体ID和第一用户的认证信息来生成第一安全密钥。 安全密钥用于加密/解密存储在第一存储设备中的内容。 安全密钥生成单元使用第二存储设备的第二媒体ID生成第一不同的安全密钥，并且使用第二用户的用户认证信息生成第二不同的安全密钥。 只有第一个安全密钥可用于解密使用第一个安全密钥加密的第一个存储设备中存储的加密内容。

    SEMICONDUCTOR MEMORY DEVICE AND DATA ERROR DETECTION AND CORRECTION METHOD OF THE SAME
    15.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND DATA ERROR DETECTION AND CORRECTION METHOD OF THE SAME 有权
    半导体存储器件及其数据错误检测及校正方法

    公开(公告)号：US20110209030A1

    公开(公告)日：2011-08-25

    申请号：US13099640

    申请日：2011-05-03

    申请人： Kwang-Jin Lee ,  Won-Seok Lee ,  Du-Eung Kim

    发明人： Kwang-Jin Lee ,  Won-Seok Lee ,  Du-Eung Kim

    IPC分类号： H03M13/05 ,  G06F11/10

    CPC分类号： G06F11/1008 ,  G06F11/1076 ,  G11C8/04 ,  G11C8/12

    摘要： A semiconductor memory device includes a memory cell array, a mode setting circuit, a parity data generation unit, and a data error detection and correction unit. The memory cell array has a plurality of first memory banks for storing normal data, and a predetermined number of second memory banks less than the number of the first memory banks for storing parity data according to control of a first flag signal. The mode setting circuit sets the first flag signal and a second flag signal controlling based on whether a separate memory bank is used to store the parity data in the second memory banks. The parity data generation unit receives normal write data during a write operation, generates parity data with respect to the normal write data in response to the second flag signal, and outputs the normal data and the parity data. The data error detection and correction unit receives normal read data and parity read data read from the memory cell array during a read operation, detects errors of the normal read data in response to the second flag signal, corrects the normal read data when the errors are detected, and outputs the corrected read data.

    摘要翻译： 半导体存储器件包括存储单元阵列，模式设置电路，奇偶校验数据生成单元和数据错误检测和校正单元。 存储单元阵列具有用于存储正常数据的多个第一存储体和小于根据第一标志信号的控制存储奇偶校验数据的第一存储体的数量的预定数量的第二存储体。 模式设置电路基于是否使用单独的存储体来存储第二存储体中的奇偶校验数据来设置第一标志信号和第二标志信号。 奇偶校验数据生成单元在写入操作期间接收正常写入数据，响应于第二标志信号生成相对于正常写入数据的奇偶校验数据，并输出正常数据和奇偶校验数据。 数据错误检测和校正单元在读取操作期间接收从存储单元阵列读取的正常读取数据和奇偶校验读取数据，响应于第二标志信号检测正常读取数据的错误，当错误为 检测并输出校正的读取数据。

    Variable resistance memory device
    16.
    发明授权
    Variable resistance memory device 有权
    可变电阻存储器件

    公开(公告)号：US07580278B2

    公开(公告)日：2009-08-25

    申请号：US11868992

    申请日：2007-10-09

    申请人： Beak-Hyung Cho ,  Jong-Soo Seo ,  Won-Seok Lee

    发明人： Beak-Hyung Cho ,  Jong-Soo Seo ,  Won-Seok Lee

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0069 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/72 ,  G11C2213/79

    摘要： A variable resistance memory device includes a memory cell array having a plurality of memory cells, a write driver which supplies a step-down set current to the memory cells, where the step-down set current includes a plurality of successive steps of decreasing current magnitude, and a set program control circuit which controls a duration of the step-down set current supplied by the write driver. The set program control circuit controls the duration of the step-down set current in accordance with at least one of data contained in an mode register set (MRS) and a conductive state of a fuse element.

    摘要翻译： 可变电阻存储器件包括具有多个存储器单元的存储单元阵列，一个写入驱动器，其将降压设定电流提供给存储器单元，其中降压设定电流包括多个连续的步骤，其降低电流幅度 以及控制由写入驱动器提供的降压设定电流的持续时间的设定程序控制电路。 设定程序控制电路根据包含在模式寄存器组（MRS）和熔丝元件的导通状态中的至少一个数据来控制降压设定电流的持续时间。

    Memory devices and memory systems having the same
    17.
    发明授权
    Memory devices and memory systems having the same 有权
    具有相同的存储器件和存储器系统

    公开(公告)号：US07535760B2

    公开(公告)日：2009-05-19

    申请号：US11902424

    申请日：2007-09-21

    申请人： Kwang-Jin Lee ,  Won-Seok Lee ,  Choong-Keun Kwak

    发明人： Kwang-Jin Lee ,  Won-Seok Lee ,  Choong-Keun Kwak

    IPC分类号： G11C14/00

    CPC分类号： H01L27/10802 ,  G11C7/00 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1084 ,  G11C11/4063 ,  H01L21/84 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841

    摘要： A non volatile memory device and a memory system having the same are disclosed. The non volatile memory device may include a memory cell array having a plurality of non volatile memory cells, a DRAM interface for exchanging data, a command and an address with an external device, a controller for selecting one of the memory cells in response to the address and performing a control operation for one of outputting data of the selected memory cell to the external device in response to the command and storing data received from the external device, and a DRAM buffer memory. The DRAM buffer memory has dynamic memory cells, and each of the dynamic memory cells has one transistor with a floating body.

    摘要翻译： 公开了一种非易失性存储器件和具有该非易失性存储器件的存储器系统。 非易失性存储器件可以包括具有多个非易失性存储器单元的存储器单元阵列，用于交换数据的DRAM接口，与外部设备的命令和地址，用于响应于所述存储器单元选择所述存储器单元中的一个的控制器 对所述存储器单元的数据的输出响应于所述命令并存储从所述外部设备接收的数据以及DRAM缓冲存储器，对所述存储单元的数据进行输出的地址和执行控制操作。 DRAM缓冲存储器具有动态存储单元，并且每个动态存储单元具有一个具有浮体的晶体管。

    Input circuit of a non-volatile semiconductor memory device
    18.
    发明申请
    Input circuit of a non-volatile semiconductor memory device 有权
    非易失性半导体存储器件的输入电路

    公开(公告)号：US20080112220A1

    公开(公告)日：2008-05-15

    申请号：US11984145

    申请日：2007-11-14

    申请人： Kwang-jin Lee ,  Won-Seok Lee ,  Qi Wang ,  Hye-Jin Kim ,  Joon Yong Choi

    发明人： Kwang-jin Lee ,  Won-Seok Lee ,  Qi Wang ,  Hye-Jin Kim ,  Joon Yong Choi

    IPC分类号： G11C16/06 ,  G11C7/00

    CPC分类号： G11C7/1078 ,  G11C7/1084 ,  G11C7/225 ,  G11C16/10

    摘要： A non-volatile semiconductor memory device may include a memory cell array that may include a plurality of memory transistors; a input circuit that may control a voltage level of an internal reference voltage and a delay time of an internal clock signal in response to an MRS trim code or an electric fuse trim code, and that may generate a first buffered input signal; a column gate that may gate the first buffered input signal in response to a decoded column address signal; and a sense amplifier that may amplify an output signal of the memory cell array to output to the column gate, and that may receive an output signal of the column gate to output to the memory cell array. The non-volatile semiconductor memory device may properly buffer an input signal of a small swing range.

    摘要翻译： 非易失性半导体存储器件可以包括可以包括多个存储晶体管的存储单元阵列; 输入电路，其可以响应于MRS修剪代码或电熔丝修剪代码来控制内部参考电压的电压电平和内部时钟信号的延迟时间，并且可以产生第一缓冲输入信号; 列门，其可以响应于解码列地址信号而选通第一缓冲输入信号; 以及读出放大器，其可以放大存储单元阵列的输出信号以输出到列门，并且可以接收列门的输出信号以输出到存储器单元阵列。 非易失性半导体存储器件可以适当地缓冲小摆动范围的输入信号。

    Variable gain low noise amplifier for a wireless terminal
    19.
    发明授权
    Variable gain low noise amplifier for a wireless terminal 有权
    用于无线终端的可变增益低噪声放大器

    公开(公告)号：US06424222B1

    公开(公告)日：2002-07-23

    申请号：US09940806

    申请日：2001-08-29

    申请人： Hoe-Sam Jeong ,  Seung-Wook Lee ,  Won-Seok Lee

    发明人： Hoe-Sam Jeong ,  Seung-Wook Lee ,  Won-Seok Lee

    IPC分类号： H03G310

    CPC分类号： H03F1/223 ,  H03F3/195 ,  H03F3/72 ,  H03F2200/294 ,  H03F2200/378 ,  H03F2200/391 ,  H03F2200/451 ,  H03F2203/7236 ,  H03G1/0088

    摘要： A variable gain, low noise amplifier is described, which is suitable as the input amplifier for a wireless terminal, or as the pre-amplifier stage of a wireless terminal transmitter. The amplifier may achieve variable gain by deploying a network of transistors in a parallel array, each independently selectable by a PMOS switch, and providing the variable resistance for the resonant circuit. Power dissipation can also be mitigated by using a network of driving transistors, each independently selectable by a PMOS switch. The resonant frequency of the amplifier may be made tunable by providing a selection of optional pull-up capacitors.

    摘要翻译： 描述了可变增益低噪声放大器，其适用于无线终端的输入放大器，或作为无线终端发射机的前置放大器级。 放大器可以通过以并联阵列布置晶体管网络来实现可变增益，每个晶体管可由PMOS开关独立选择，并为谐振电路提供可变电阻。 也可以通过使用驱动晶体管的网络来减轻功耗，每个驱动晶体管都可以由PMOS开关独立选择。 可以通过提供可选的上拉电容器的选择来使放大器的谐振频率可调。