公开(公告)号：US08625383B2

公开(公告)日：2014-01-07

申请号：US13736501

申请日：2013-01-08

申请人： Hung-Chang Yu ,  Yue-Der Chih

发明人： Hung-Chang Yu ,  Yue-Der Chih

IPC分类号： G11C8/00

CPC分类号： G11C5/14 ,  G11C7/10 ,  G11C8/08 ,  G11C16/08

摘要： A memory including a boost circuit configured to supply a voltage higher than a supply voltage to a word line. The boost circuit includes a first capacitor having a first capacitor dielectric thickness. The boost circuit further includes a transmission gate coupled to the word line and the first capacitor, the transmission gate having a gate-dielectric thickness that is greater than the first capacitor dielectric thickness.

摘要翻译： 包括升压电路的存储器，被配置为向字线提供高于电源电压的电压。 升压电路包括具有第一电容器介电厚度的第一电容器。 升压电路还包括耦合到字线和第一电容器的传输门，传输门具有大于第一电容器电介质厚度的栅介电厚度。

公开(公告)号：US08369180B2

公开(公告)日：2013-02-05

申请号：US12949261

申请日：2010-11-18

申请人： Hung-Chang Yu ,  Yue-Der Chih

发明人： Hung-Chang Yu ,  Yue-Der Chih

IPC分类号： G11C8/00

CPC分类号： G11C5/14 ,  G11C7/10 ,  G11C8/08 ,  G11C16/08

摘要： A memory includes a word line and a word line boost circuit. The word line boost circuit includes a capacitor having a capacitor dielectric thickness, and a transmission gate coupled to the word line and the capacitor. The transmission gate has a gate-dielectric thickness that is greater than the capacitor dielectric thickness. The word line boost circuit is configured to supply a high voltage that is higher than a power supply voltage to the word line during an operation of the memory by utilizing the capacitor.

摘要翻译： 存储器包括字线和字线升压电路。 字线升压电路包括具有电容器电介质厚度的电容器，以及耦合到字线和电容器的传输栅极。 传输栅极具有大于电容器电介质厚度的栅介质厚度。 字线升压电路被配置为通过利用电容器在存储器的操作期间向字线提供高于电源电压的高电压。

公开(公告)号：US08817553B2

公开(公告)日：2014-08-26

申请号：US13052637

申请日：2011-03-21

申请人： Hung-Chang Yu ,  Yue-Der Chih

发明人： Hung-Chang Yu ,  Yue-Der Chih

IPC分类号： G11C7/06 ,  G11C5/14 ,  G11C7/10 ,  G11C8/08

CPC分类号： G11C5/145 ,  G11C5/147 ,  G11C7/12 ,  G11C8/08

摘要： A memory includes a word line having a word line voltage, a charge pump coupled to the word line, and a dynamic feedback control circuit coupled to the charge pump. The dynamic feedback control circuit is capable of changing a clock frequency of a clock signal supplied the charge pump from a first non-zero value to a second non-zero value depending on the difference between the word line voltage and a target threshold voltage.

摘要翻译： 存储器包括具有字线电压的字线，耦合到字线的电荷泵和耦合到电荷泵的动态反馈控制电路。 动态反馈控制电路能够根据字线电压和目标阈值电压之间的差异，将提供给电荷泵的时钟信号的时钟频率从第一非零值改变为第二非零值。

公开(公告)号：US08570792B2

公开(公告)日：2013-10-29

申请号：US13356920

申请日：2012-01-24

申请人： Tien-Wei Chiang ,  Kai-Chun Lin ,  Ya-Chen Kao ,  Hung-Chang Yu

发明人： Tien-Wei Chiang ,  Kai-Chun Lin ,  Ya-Chen Kao ,  Hung-Chang Yu

IPC分类号： G11C11/00 ,  G11C11/14

CPC分类号： H01L27/222 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  H01L43/08

摘要： A magnetoresistive random access memory (MRAM) cell includes a magnetic tunnel junction (MTJ), a top electrode disposed over the MTJ, a bottom electrode disposed below the MTJ, and an induction line disposed above or below the MTJ. The induction line is configured to induce a magnetic field at the MTJ.

摘要翻译： 磁阻随机存取存储器（MRAM）单元包括磁性隧道结（MTJ），设置在MTJ上方的顶部电极，设置在MTJ下方的底部电极以及设置在MTJ上方或下方的感应线。 感应线被配置为在MTJ处诱导磁场。

公开(公告)号：US08384471B2

公开(公告)日：2013-02-26

申请号：US12945543

申请日：2010-11-12

申请人： Hung-Chang Yu

发明人： Hung-Chang Yu

IPC分类号： G05F3/26 ,  G05F3/24

CPC分类号： G05F3/242

摘要： A circuit includes a first PMOS transistor and a second PMOS transistor, wherein a gate of the second PMOS transistor is coupled to a gate and a drain of the first PMOS transistor; a first NMOS transistor having a drain coupled to a drain of the first PMOS transistor; and a second NMOS transistor, wherein a drain of the second NMOS transistor is coupled to a gate of the first NMOS transistor, a gate of the second NMOS transistor, and a drain of the second PMOS transistor. A first switch is coupled between the drain of the first PMOS transistor and the drain of the second PMOS transistor. A second switch is coupled between a source of the first NMOS transistor and an electrical ground. A third switch is coupled between a source of the second NMOS transistor and the electrical ground.

摘要翻译： 电路包括第一PMOS晶体管和第二PMOS晶体管，其中第二PMOS晶体管的栅极耦合到第一PMOS晶体管的栅极和漏极; 第一NMOS晶体管，具有耦合到第一PMOS晶体管的漏极的漏极; 以及第二NMOS晶体管，其中第二NMOS晶体管的漏极耦合到第一NMOS晶体管的栅极，第二NMOS晶体管的栅极和第二PMOS晶体管的漏极。 第一开关耦合在第一PMOS晶体管的漏极和第二PMOS晶体管的漏极之间。 第二开关耦合在第一NMOS晶体管的源极和电接地之间。 第三开关耦合在第二NMOS晶体管的源极和电接地之间。

公开(公告)号：US07062738B1

公开(公告)日：2006-06-13

申请号：US10205518

申请日：2002-07-25

申请人： Kwan-Jen Chu ,  Hung-Chang Yu

发明人： Kwan-Jen Chu ,  Hung-Chang Yu

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5068 ,  G11C16/30

摘要： This invention provides a compiler, circuits and a method for generating a flash memory for integrated circuits. This invention provides a flash memory compiler which can generate flexible configurations which are a function of the flash memory array bit count. In addition, this flash compiler of this invention has the ability to optimize the resultant flash memories so as to produce the correct amount of flash array current driving capability and minimal wasting of power dissipation as a function of the flash memory array size.

摘要翻译： 本发明提供了一种用于集成电路的闪速存储器的编译器，电路和方法。 本发明提供了一种闪存编译器，其可以产生作为闪速存储器阵列位数的函数的灵活配置。 此外，本发明的该闪存编译器具有优化所得到的闪速存储器的能力，以便产生正确数量的闪存阵列电流驱动能力，并且作为闪速存储器阵列尺寸的函数的功耗最小化。

公开(公告)号：US06127853A

公开(公告)日：2000-10-03

申请号：US224296

申请日：1998-12-31

申请人： Hung-Chang Yu

发明人： Hung-Chang Yu

IPC分类号： G11C7/06

CPC分类号： G11C7/067 ,  G11C2207/063

摘要： A current-direction sense-amplifier circuit for amplifying data signal read out from a bit-line of memory cells is disclosed. The current-direction sense-amplifier circuit includes two positive feedback loop circuits coupled each other. The first positive feedback loop circuit which having a data input terminal for receiving the data signal, first output node, and second output node for amplifying a differential voltage between a voltage of the first output node and a voltage of the second output node. The second positive feedback loop circuits being coupled with the first positive feedback loop circuit at the first output node and second output node of node so as to enlarge the loop voltage gain and make the increment and the decrement of voltage swing more symmetrical.

摘要翻译： 公开了用于放大从存储器单元的位线读出的数据信号的电流方向读出放大器电路。 电流方向读出放大器电路包括彼此耦合的两个正反馈回路电路。 第一正反馈环路电路具有用于接收数据信号的数据输入端子，第一输出节点和用于放大第一输出节点的电压和第二输出节点的电压之间的差分电压的第二输出节点。 第二正反馈回路与节点的第一输出节点和第二输出节点处的第一正反馈回路耦合，以便增大回路电压增益，并使电压摆幅的增量和减小更对称。

公开(公告)号：US06594812B2

公开(公告)日：2003-07-15

申请号：US09918008

申请日：2001-07-30

申请人： Chien-Fan Wang ,  Hung-Chang Yu

发明人： Chien-Fan Wang ,  Hung-Chang Yu

IPC分类号： G06F1750

CPC分类号： H03K19/1776 ,  G11C17/00 ,  H01L27/112 ,  H03K19/17796

摘要： A method and system for forming a programmable logic array from a plurality of read only memory cells. The interconnection of the first metal layer with a second metal layer results in the formation of a read only memory cell therebetween, such that a plurality of read only memory cells can be configured to form a programmable logic array. One or more of the read only memory cells may be programmed utilizing a particular contact via programming technique, resulting in a shortened turn-around-time, reduced read only memory cell size, and a reduction in the necessity of requiring additional masks for read only memory logical processes associated with the programmable logic array. The memory cells comprise mask ROM cells which do not require extra masks, and can be programmed utilizing via programming techniques. The utilization of a first and second metal layer in interconnection configuration for a ROM cell results in smaller cell size.

摘要翻译： 一种用于从多个只读存储器单元形成可编程逻辑阵列的方法和系统。 第一金属层与第二金属层的互连导致在其间形成只读存储单元，使得可以将多个只读存储器单元配置成形成可编程逻辑阵列。 一个或多个只读存储器单元可以使用经由编程技术的特定接触器进行编程，导致缩短的周转时间，减小的只读存储器单元尺寸以及需要额外的掩模用于只读的必要性 与可编程逻辑阵列相关联的存储器逻辑进程。 存储器单元包括不需要额外掩模的掩模ROM单元，并且可以使用通过编程技术编程。 在ROM单元的互连配置中利用第一和第二金属层导致更小的单元尺寸。

公开(公告)号：US20140064000A1

公开(公告)日：2014-03-06

申请号：US13600867

申请日：2012-08-31

申请人： Hung-Chang Yu ,  Ku-Feng Lin

发明人： Hung-Chang Yu ,  Ku-Feng Lin

IPC分类号： G11C7/12

CPC分类号： G11C7/12 ,  G11C11/4094 ,  G11C2207/002 ,  G11C2207/005

摘要： A device includes a first switch configured to control a connection between a first voltage node and a capacitor, and a second switch configured to control a connection between a common charge node and the capacitor. The device further includes a plurality of bit-lines, and a plurality of bit-line charge switches, each configured to control a connection between a respective one of the plurality of bit-lines and the common charge node.

摘要翻译： 一种设备包括被配置为控制第一电压节点和电容器之间的连接的第一开关和被配置为控制公共电荷节点和电容器之间的连接的第二开关。 该装置还包括多个位线和多个位线充电开关，每个位线充电开关被配置为控制多个位线中的相应一个位线和公共电荷节点之间的连接。

公开(公告)号：US09177621B2

公开(公告)日：2015-11-03

申请号：US13600867

申请日：2012-08-31

申请人： Hung-Chang Yu ,  Ku-Feng Lin

发明人： Hung-Chang Yu ,  Ku-Feng Lin

IPC分类号： G11C7/00 ,  G11C7/12 ,  G11C11/4094

CPC分类号： G11C7/12 ,  G11C11/4094 ,  G11C2207/002 ,  G11C2207/005

摘要： A device includes a first switch configured to control a connection between a first voltage node and a capacitor, and a second switch configured to control a connection between a common charge node and the capacitor. The device further includes a plurality of bit-lines, and a plurality of bit-line charge switches, each configured to control a connection between a respective one of the plurality of bit-lines and the common charge node.

摘要翻译： 器件包括被配置为控制第一电压节点和电容器之间的连接的第一开关和被配置为控制公共电荷节点和电容器之间的连接的第二开关。 该装置还包括多个位线和多个位线充电开关，每个位线充电开关被配置为控制多个位线中的相应一个位线和公共电荷节点之间的连接。