公开(公告)号：US08842489B2

公开(公告)日：2014-09-23

申请号：US13447318

申请日：2012-04-16

申请人： Hung-Chang Yu ,  Ku-Feng Lin ,  Kai-Chun Lin ,  Yue-Der Chih

发明人： Hung-Chang Yu ,  Ku-Feng Lin ,  Kai-Chun Lin ,  Yue-Der Chih

IPC分类号： G11C5/14

CPC分类号： G11C11/418 ,  G11C8/08 ,  G11C11/4085

摘要： A word line driver of a semiconductor memory includes logic circuitry for coupling a word line to a first node set at a first voltage level when the word line driver is in a first state or to a second node set at a second voltage level when the word line driver is in a second state. A capacitor is configured to be charged to a third voltage level that is greater than the first and second voltage levels. First and second transistors are configured to selectively couple the word line to the capacitor and to a third node set at a fourth voltage level when the word line driver is in a third state. The fourth voltage level is greater than the first voltage level and less than the second voltage level.

摘要翻译： 半导体存储器的字线驱动器包括逻辑电路，用于当字线驱动器处于第一状态时将字线耦合到设置在第一电压电平处的第一节点，或者当字线驱动器处于第二电压电平时将字线耦合到设置为第二电压电平的第二节点 线路驱动器处于第二状态。 电容器被配置为被充电到大于第一和第二电压电平的第三电压电平。 第一和第二晶体管被配置为当字线驱动器处于第三状态时，将字线选择性地耦合到电容器和设置在第四电压电平的第三节点。 第四电压电平大于第一电压电平并小于第二电压电平。

公开(公告)号：US20140064000A1

公开(公告)日：2014-03-06

申请号：US13600867

申请日：2012-08-31

申请人： Hung-Chang Yu ,  Ku-Feng Lin

发明人： Hung-Chang Yu ,  Ku-Feng Lin

IPC分类号： G11C7/12

CPC分类号： G11C7/12 ,  G11C11/4094 ,  G11C2207/002 ,  G11C2207/005

摘要： A device includes a first switch configured to control a connection between a first voltage node and a capacitor, and a second switch configured to control a connection between a common charge node and the capacitor. The device further includes a plurality of bit-lines, and a plurality of bit-line charge switches, each configured to control a connection between a respective one of the plurality of bit-lines and the common charge node.

摘要翻译： 一种设备包括被配置为控制第一电压节点和电容器之间的连接的第一开关和被配置为控制公共电荷节点和电容器之间的连接的第二开关。 该装置还包括多个位线和多个位线充电开关，每个位线充电开关被配置为控制多个位线中的相应一个位线和公共电荷节点之间的连接。

公开(公告)号：US09177621B2

公开(公告)日：2015-11-03

申请号：US13600867

申请日：2012-08-31

申请人： Hung-Chang Yu ,  Ku-Feng Lin

发明人： Hung-Chang Yu ,  Ku-Feng Lin

IPC分类号： G11C7/00 ,  G11C7/12 ,  G11C11/4094

CPC分类号： G11C7/12 ,  G11C11/4094 ,  G11C2207/002 ,  G11C2207/005

摘要： A device includes a first switch configured to control a connection between a first voltage node and a capacitor, and a second switch configured to control a connection between a common charge node and the capacitor. The device further includes a plurality of bit-lines, and a plurality of bit-line charge switches, each configured to control a connection between a respective one of the plurality of bit-lines and the common charge node.

摘要翻译： 器件包括被配置为控制第一电压节点和电容器之间的连接的第一开关和被配置为控制公共电荷节点和电容器之间的连接的第二开关。 该装置还包括多个位线和多个位线充电开关，每个位线充电开关被配置为控制多个位线中的相应一个位线和公共电荷节点之间的连接。

公开(公告)号：US08964458B2

公开(公告)日：2015-02-24

申请号：US13446250

申请日：2012-04-13

申请人： Kai-Chun Lin ,  Hung-Chang Yu ,  Yue-Der Chih ,  Chun-Jung Lin

发明人： Kai-Chun Lin ,  Hung-Chang Yu ,  Yue-Der Chih ,  Chun-Jung Lin

IPC分类号： G11C11/16

CPC分类号： G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C29/74

摘要： A magnetoresistive memory has first and second magnetic tunnel junction (MTJ) elements operated differentially, each with a pinned magnetic layer and a free magnetic layer that can have field alignments that are parallel or anti-parallel, producing differential high and low resistance states representing a bit cell value. Writing a high resistance state to an element requires an opposite write current polarity through the pinned and free layers, and differential operation requires that the two MTJ elements be written to different resistance states. One aspect is to arrange or connect the layers in normal and reverse order relative to a current bias source, thereby achieving opposite write current polarities relative to the layers using the same current polarity relative to the current bias source. The differentially operated MTJ elements can supplement or replace single MTJ elements in a nonvolatile memory bit cell array.

摘要翻译： 磁阻存储器具有差分地操作的第一和第二磁性隧道结（MTJ）元件，每个具有钉扎磁性层和可以具有并联或反平行的场对准的自由磁性层，产生表示 位单元格值。 向元件写入高电阻状态需要通过固定和自由层的相反的写入电流极性，并且差分操作要求将两个MTJ元件写入不同的电阻状态。 一个方面是相对于电流偏置源以正常和相反的顺序布置或连接层，从而相对于使用相对于电流偏置源的相同电流极性的层获得相反的写入电流极性。 差分操作的MTJ元件可以补充或替代非易失性存储器位单元阵列中的单个MTJ元件。

公开(公告)号：US08654589B2

公开(公告)日：2014-02-18

申请号：US12970123

申请日：2010-12-16

申请人： Hung-Chang Yu ,  Yue-Der Chih

发明人： Hung-Chang Yu ,  Yue-Der Chih

IPC分类号： G11C7/00

CPC分类号： G11C5/145 ,  G11C5/147 ,  G11C7/12 ,  G11C8/08

摘要： A memory includes a word line, a charge pump coupled to the word line, and a charge pump control circuit coupled to the charge pump. The charge pump control circuit is configured to turn on the charge pump if the word line voltage is lower than a first threshold voltage and turn off the charge pump if the word line voltage is higher than a second threshold voltage.

摘要翻译： 存储器包括字线，耦合到字线的电荷泵和耦合到电荷泵的电荷泵控制电路。 如果字线电压低于第一阈值电压，则电荷泵控制电路被配置为接通电荷泵，如果字线电压高于第二阈值电压，则关闭电荷泵。

公开(公告)号：US08625383B2

公开(公告)日：2014-01-07

申请号：US13736501

申请日：2013-01-08

申请人： Hung-Chang Yu ,  Yue-Der Chih

发明人： Hung-Chang Yu ,  Yue-Der Chih

IPC分类号： G11C8/00

CPC分类号： G11C5/14 ,  G11C7/10 ,  G11C8/08 ,  G11C16/08

摘要： A memory including a boost circuit configured to supply a voltage higher than a supply voltage to a word line. The boost circuit includes a first capacitor having a first capacitor dielectric thickness. The boost circuit further includes a transmission gate coupled to the word line and the first capacitor, the transmission gate having a gate-dielectric thickness that is greater than the first capacitor dielectric thickness.

摘要翻译： 包括升压电路的存储器，被配置为向字线提供高于电源电压的电压。 升压电路包括具有第一电容器介电厚度的第一电容器。 升压电路还包括耦合到字线和第一电容器的传输门，传输门具有大于第一电容器电介质厚度的栅介电厚度。

公开(公告)号：US20130201754A1

公开(公告)日：2013-08-08

申请号：US13364756

申请日：2012-02-02

申请人： Hung-Chang Yu ,  Kai-Chun Lin ,  Yue-Der Chih ,  Chun-Jung Lin

发明人： Hung-Chang Yu ,  Kai-Chun Lin ,  Yue-Der Chih ,  Chun-Jung Lin

IPC分类号： G11C11/16

CPC分类号： G11C11/1673 ,  G11C13/004 ,  G11C29/74

摘要： A magnetoresistive memory stores logic values in high and low resistance states of magnetic tunnel junction elements. Instead of comparing the resistance of elements to a fixed threshold to discern a logic state, the resistances of elements are self-compared before and after imposing a low resistance state. A measure of the resistance of an element in its unknown resistance state is stored, for example by charging a capacitor to a voltage produced when read current bias is applied. Then the element is written into its low resistance state and read current bias is applied again to develop another voltage, representing the low resistance state. A comparison circuit using current summing and an offset providing a minimum difference tolerance determines whether the resistance of the element was changed or remained the same. This determines the logic state of the element.

摘要翻译： 磁阻存储器将逻辑值存储在磁性隧道结元件的高电阻和低电阻状态中。 代替将元件的电阻与固定阈值进行比较以辨别逻辑状态，元件的电阻在施加低电阻状态之前和之后自我比较。 例如，通过将电容器充电到施加读取电流偏压时产生的电压来存储元件在其未知电阻状态下的电阻的量度。 然后将元件写入其低电阻状态，并再次施加读取电流偏压以产生表示低电阻状态的另一电压。 使用电流求和和提供最小差容差的偏移的比较电路确定元件的电阻是改变还是保持相同。 这决定了元素的逻辑状态。

公开(公告)号：US08384471B2

公开(公告)日：2013-02-26

申请号：US12945543

申请日：2010-11-12

申请人： Hung-Chang Yu

发明人： Hung-Chang Yu

IPC分类号： G05F3/26 ,  G05F3/24

CPC分类号： G05F3/242

摘要： A circuit includes a first PMOS transistor and a second PMOS transistor, wherein a gate of the second PMOS transistor is coupled to a gate and a drain of the first PMOS transistor; a first NMOS transistor having a drain coupled to a drain of the first PMOS transistor; and a second NMOS transistor, wherein a drain of the second NMOS transistor is coupled to a gate of the first NMOS transistor, a gate of the second NMOS transistor, and a drain of the second PMOS transistor. A first switch is coupled between the drain of the first PMOS transistor and the drain of the second PMOS transistor. A second switch is coupled between a source of the first NMOS transistor and an electrical ground. A third switch is coupled between a source of the second NMOS transistor and the electrical ground.

摘要翻译： 电路包括第一PMOS晶体管和第二PMOS晶体管，其中第二PMOS晶体管的栅极耦合到第一PMOS晶体管的栅极和漏极; 第一NMOS晶体管，具有耦合到第一PMOS晶体管的漏极的漏极; 以及第二NMOS晶体管，其中第二NMOS晶体管的漏极耦合到第一NMOS晶体管的栅极，第二NMOS晶体管的栅极和第二PMOS晶体管的漏极。 第一开关耦合在第一PMOS晶体管的漏极和第二PMOS晶体管的漏极之间。 第二开关耦合在第一NMOS晶体管的源极和电接地之间。 第三开关耦合在第二NMOS晶体管的源极和电接地之间。

公开(公告)号：US07062738B1

公开(公告)日：2006-06-13

申请号：US10205518

申请日：2002-07-25

申请人： Kwan-Jen Chu ,  Hung-Chang Yu

发明人： Kwan-Jen Chu ,  Hung-Chang Yu

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5068 ,  G11C16/30

摘要： This invention provides a compiler, circuits and a method for generating a flash memory for integrated circuits. This invention provides a flash memory compiler which can generate flexible configurations which are a function of the flash memory array bit count. In addition, this flash compiler of this invention has the ability to optimize the resultant flash memories so as to produce the correct amount of flash array current driving capability and minimal wasting of power dissipation as a function of the flash memory array size.

摘要翻译： 本发明提供了一种用于集成电路的闪速存储器的编译器，电路和方法。 本发明提供了一种闪存编译器，其可以产生作为闪速存储器阵列位数的函数的灵活配置。 此外，本发明的该闪存编译器具有优化所得到的闪速存储器的能力，以便产生正确数量的闪存阵列电流驱动能力，并且作为闪速存储器阵列尺寸的函数的功耗最小化。

公开(公告)号：US06127853A

公开(公告)日：2000-10-03

申请号：US224296

申请日：1998-12-31

申请人： Hung-Chang Yu

发明人： Hung-Chang Yu

IPC分类号： G11C7/06

CPC分类号： G11C7/067 ,  G11C2207/063

摘要： A current-direction sense-amplifier circuit for amplifying data signal read out from a bit-line of memory cells is disclosed. The current-direction sense-amplifier circuit includes two positive feedback loop circuits coupled each other. The first positive feedback loop circuit which having a data input terminal for receiving the data signal, first output node, and second output node for amplifying a differential voltage between a voltage of the first output node and a voltage of the second output node. The second positive feedback loop circuits being coupled with the first positive feedback loop circuit at the first output node and second output node of node so as to enlarge the loop voltage gain and make the increment and the decrement of voltage swing more symmetrical.

摘要翻译： 公开了用于放大从存储器单元的位线读出的数据信号的电流方向读出放大器电路。 电流方向读出放大器电路包括彼此耦合的两个正反馈回路电路。 第一正反馈环路电路具有用于接收数据信号的数据输入端子，第一输出节点和用于放大第一输出节点的电压和第二输出节点的电压之间的差分电压的第二输出节点。 第二正反馈回路与节点的第一输出节点和第二输出节点处的第一正反馈回路耦合，以便增大回路电压增益，并使电压摆幅的增量和减小更对称。