-
公开(公告)号：US20120169580A1
公开(公告)日：2012-07-05
申请号：US13395716
申请日：2010-05-18
IPC分类号： G09G3/36
CPC分类号： G09G3/3618 , G09G3/3614 , G09G3/3659 , G09G2300/0823 , G09G2300/0852
摘要： A memory liquid crystal display device includes a transistor (N1), a transistor (N2), a transistor (N3), a transistor (N4), a first storage capacitor (storage capacitor of an overlapping part of a capacitor electrode 37a and a CS line CSL(i)) connected to a pixel electrode (7), and a second storage capacitor (storage capacitor of an overlapping part of a capacitor electrode 37b and a CS extension section 10bb) connected to the pixel electrode (7) via the transistor (N2), the pixel electrode (7) being connected to (a) a source line (SL(j)) via the transistor (N1), (b) a data transfer control line (DT(i)) via the transistor (N4) and the third transistor, (c) a drain electrode (9a) of the transistor (N1) via a contact hole (13), and (d) a source electrode (8b) of the transistor (N2) and to a drain electrode (9c) of the transistor (N4), via a contact hole (14). This allows for improving a yield rate and for reducing malfunction caused by noise generated between signal lines, in a memory liquid crystal display device.
摘要翻译： 存储液晶显示装置包括晶体管（N1），晶体管（N2），晶体管（N3），晶体管（N4），第一存储电容器（电容器电极37a的重叠部分的存储电容器和CS 连接到像素电极（7）的线CSL（i））和连接到像素电极（7）的第二存储电容器（电容器电极37b和CS延伸部分10bb的重叠部分的存储电容器） （N2），经由晶体管（N1）与（a）源极线（SL（j））连接的像素电极（7），（b）经由晶体管的数据传输控制线（DT（i） N4）和第三晶体管，（c）经由接触孔（13）的晶体管（N1）的漏电极（9a）和（d）晶体管（N2）的源电极（8b）和漏极 晶体管（N4）的电极（9c）经由接触孔（14）。 这允许在存储器液晶显示装置中提高成品率并减少由信号线之间产生的噪声引起的故障。
-
12.发明申请公开(公告)号：US20120169579A1
公开(公告)日：2012-07-05
申请号：US13395549
申请日：2010-05-18
CPC分类号： H01L27/108 , G09G3/3614 , G09G3/3618 , G09G3/3648 , G09G3/3659 , G09G2300/0823 , G09G2300/0852 , G09G2330/021 , G11C11/406 , G11C2211/4067 , H01L27/12
摘要： A transistor (N1) has a gate terminal connected to a word line (Xi(1)) and a first conduction terminal connected to a bit line (Yj). A transistor (N2) has a gate terminal connected to the word line (Xi(2)) and a first conduction terminal connected to a node (PIX). A transistor (N3) has a gate terminal connected to a node (MRY) and a first conduction terminal connected to the word line (Xi(2)). A transistor (N4) has a gate terminal connected to the word line (Xi(3)), a first conduction terminal connected to a second conduction terminal of the transistor (N3), and a second conduction terminal connected to the node (PIX). Capacitors (Ca1), (Cb1), (Cap1) are formed between the node (PIX) and a reference electric potential wire (RL1), between the node (MRY) and the reference electric potential wire (RL1), and between the first conduction terminal of the transistor (N3) and the node (MRY), respectively.
摘要翻译： 晶体管（N1）具有连接到字线（Xi（1））的栅极端子和连接到位线（Yj）的第一导电端子。 晶体管（N2）具有连接到字线（Xi（2））的栅极端子和连接到节点（PIX）的第一导电端子。 晶体管（N3）具有连接到节点（MRY）的栅极端子和连接到字线（Xi（2））的第一导电端子。 晶体管（N4）具有连接到字线（Xi（3））的栅极端子，连接到晶体管（N3）的第二导通端子的第一导电端子和连接到节点（PIX）的第二导电端子， 。 在节点（MRY）和参考电位线（RL1）之间以及在第一（VI））之间的节点（PIX）和参考电位线（RL1）之间形成电容器（Ca1），（Cb1） 晶体管（N3）和节点（MRY）的导通端子。
-
公开(公告)号：US08896511B2
公开(公告)日：2014-11-25
申请号：US13395681
申请日：2010-05-18
申请人： Etsuo Yamamoto , Yasushi Sasaki , Yuhichiroh Murakami , Shige Furuta , Seijirou Gyouten , Shuji Nishi
发明人： Etsuo Yamamoto , Yasushi Sasaki , Yuhichiroh Murakami , Shige Furuta , Seijirou Gyouten , Shuji Nishi
IPC分类号： G09G3/36 , G09G5/00 , G02F1/1362
CPC分类号： G09G3/3648 , G02F1/13624 , G09G3/3614 , G09G2300/0857 , G09G2310/08 , G09G2320/0219 , G09G2330/021
摘要： In an active matrix display apparatus including: pixels provided in a matrix pattern, the pixels each including a memory circuit which retains data while refreshing the data, a data signal electric potential which is supplied from a source line in a period t1 and written to a node which is connected to a liquid capacitor is higher than a data electric potential of the node, the data electric potential being obtained in a period t14 after a refresh operation of the memory circuit.
摘要翻译： 在一种有源矩阵显示装置中，包括以矩阵模式提供的像素，每个像素包括一个在刷新数据的同时保留数据的存储电路，在时间段t1内从源极线提供的数据信号电位被写入到 连接到液体电容器的节点高于节点的数据电位，在存储器电路的刷新操作之后的周期t14中获得数据电位。
-
公开(公告)号：US08866720B2
公开(公告)日：2014-10-21
申请号：US13496027
申请日：2010-04-23
IPC分类号： G09G5/36 , G11C11/405 , G09G3/36
CPC分类号： G09G3/3659 , G09G2300/0417 , G09G2300/0823 , G09G2300/0842 , G09G2300/0861 , G09G2300/088 , G09G2330/022 , G11C11/405
摘要： A memory device is provided which includes a memory circuit that allows a circuit which carries out a refresh operation to suitably carry out an original operation of the circuit even if an off-leakage current occurs in a transfer element used in a transfer section. A memory cell includes a switching circuit, a first retaining section, a transfer section, a second retaining section, a first control section, and a voltage supply, and the first control section is controlled to be in (i) a state in which the first control section carries out a first operation in which the first control section is in an active state or a non-active state and (ii) a state in which the first control section carries out a second operation.
摘要翻译： 提供了一种存储器件，其包括一个存储器电路，即使在转印部件中使用的转印元件中出现泄漏电流，允许进行刷新操作的电路适当地执行电路的原始操作。 存储单元包括开关电路，第一保持部分，转移部分，第二保持部分，第一控制部分和电压源，并且第一控制部分被控制为处于（i） 第一控制部分执行第一操作，其中第一控制部分处于活动状态或非活动状态，以及（ii）第一控制部分执行第二操作的状态。
-
公开(公告)号：US08860646B2
公开(公告)日：2014-10-14
申请号：US13395716
申请日：2010-05-18
IPC分类号： G09G3/36
CPC分类号： G09G3/3618 , G09G3/3614 , G09G3/3659 , G09G2300/0823 , G09G2300/0852
摘要： A memory liquid crystal display device includes a transistor (N1), a transistor (N2), a transistor (N3), a transistor (N4), a first storage capacitor (storage capacitor of an overlapping part of a capacitor electrode 37a and a CS line CSL(i)) connected to a pixel electrode (7), and a second storage capacitor (storage capacitor of an overlapping part of a capacitor electrode 37b and a CS extension section 10bb) connected to the pixel electrode (7) via the transistor (N2), the pixel electrode (7) being connected to (a) a source line (SL(j)) via the transistor (N1), (b) a data transfer control line (DT(i)) via the transistor (N4) and the third transistor, (c) a drain electrode (9a) of the transistor (N1) via a contact hole (13), and (d) a source electrode (8b) of the transistor (N2) and to a drain electrode (9c) of the transistor (N4), via a contact hole (14). This allows for improving a yield rate and for reducing malfunction caused by noise generated between signal lines, in a memory liquid crystal display device.
摘要翻译： 存储液晶显示装置包括晶体管（N1），晶体管（N2），晶体管（N3），晶体管（N4），第一存储电容器（电容器电极37a的重叠部分的存储电容器和CS 连接到像素电极（7）的线CSL（i））和连接到像素电极（7）的第二存储电容器（电容器电极37b和CS延伸部分10bb的重叠部分的存储电容器） （N2），经由晶体管（N1）与（a）源极线（SL（j））连接的像素电极（7），（b）经由晶体管的数据传输控制线（DT（i） N4）和第三晶体管，（c）经由接触孔（13）的晶体管（N1）的漏电极（9a）和（d）晶体管（N2）的源电极（8b）和漏极 晶体管（N4）的电极（9c）经由接触孔（14）。 这允许在存储器液晶显示装置中提高成品率并减少由信号线之间产生的噪声引起的故障。
-
公开(公告)号：US08791895B2
公开(公告)日：2014-07-29
申请号：US13395536
申请日：2010-05-26
申请人： Makoto Yokoyama , Shige Furuta , Yuhichiroh Murakami , Yasushi Sasaki , Seijirou Gyouten , Shuji Nishi
发明人： Makoto Yokoyama , Shige Furuta , Yuhichiroh Murakami , Yasushi Sasaki , Seijirou Gyouten , Shuji Nishi
IPC分类号： G09G3/36
CPC分类号： G09G3/3648 , G02F1/13624 , G09G2300/043 , G09G2300/0819 , G09G2300/0852 , G09G2300/0876 , G09G2310/063 , G09G2310/08 , G09G2320/0219 , G09G2320/0247 , G09G2340/0428
摘要： In a memory liquid crystal display device, a potential of a storage capacitor line signal (CS) supplied to the CS lines (CSL(i)) are once decreased (ΔVcs) while the gate lines (GL(i)) are made simultaneously active (period t4, period t10) in the data holding period (T2), and the potential of the storage capacitor line signal (CS) is made back to its original potential while the gate lines (GL(i)) are made simultaneously inactive and the refresh output control lines (RC(i)) are made active (period t5, period t11). This reduces flicker, thereby allowing for improvement in display quality of the memory liquid crystal display device.
摘要翻译： 在存储器液晶显示装置中，提供给CS线（CSL（i））的辅助电容配线信号（CS）的电位在制作栅极线（GL（i））时一度减小（＆Dgr; Vcs） 在数据保持期间（T2）中同时有效（周期t4，期间t10），并且保持电容配线信号（CS）的电位恢复到原来的电位，而同时进行栅极线（GL（i）） 并且刷新输出控制线（RC（i））被激活（时段t5，周期t11）。 这减少了闪烁，从而可以提高存储器液晶显示装置的显示质量。
-
公开(公告)号：US08743042B2
公开(公告)日：2014-06-03
申请号：US13395697
申请日：2010-04-23
CPC分类号： G09G3/3607 , G09G3/3614 , G09G3/3618 , G09G3/3655 , G09G3/3659 , G09G2300/0814 , G09G2300/0823 , G09G2300/0842 , G09G2300/0852 , G09G2300/0861 , G09G2320/0219 , G09G2330/021 , G09G2330/022
摘要： Provided are a display device capable of preventing image noise arising from changes in potential of a common electrode and auxiliary capacitor lines at the time of a switch between a normal mode and a memory mode and a method for driving such a display device. In a case where it is necessary to cause the common electrode and the auxiliary capacitor lines to change in potential along with a switch between the normal mode and the memory mode, the change in potential is made while electrically connecting a node of each memory circuit to a corresponding source line with the corresponding source line having its potential fixed and with the memory circuit having its a switch circuit in a conductive state.
摘要翻译： 提供了能够防止在正常模式和存储模式之间的切换时由公共电极和辅助电容器线的电位变化引起的图像噪声的显示装置以及用于驱动这种显示装置的方法。 在需要使公共电极和辅助电容线与正常模式和存储模式之间的切换一起改变电位的情况下，在将每个存储器电路的节点电连接到 对应的源极线，其相应的源极线具有其电位固定，并且存储电路具有其导通状态的开关电路。
-
18.发明申请公开(公告)号：US20120306829A1
公开(公告)日：2012-12-06
申请号：US13575490
申请日：2011-02-10
CPC分类号： G11C19/28 , G09G3/3677
摘要： A shift register includes a plurality of stages of unit circuits each including a flip-flop. Each of the unit circuits generates, by obtaining a sync signal in accordance with an output from the flip-flop, an output signal. The flip-flop includes a first switch and a second switch and a latch circuit for latching a signal supplied thereto and outputting the signal as the output from the flip-flop. A first shift direction signal is supplied to the latch circuit via the first switch, and the second shift direction signal is supplied to the latch circuit via the second switch. In each unit circuit other than those of the first and last stages, an output signal from a previous stage is supplied to a control terminal of the first switch, and an output signal from a subsequent stage is supplied to a control terminal of the second switch.
摘要翻译： 移位寄存器包括多个阶段的单元电路，每个单元电路包括一个触发器。 每个单元电路通过根据触发器的输出获得同步信号来产生输出信号。 触发器包括第一开关和第二开关以及用于锁存提供给其的信号的锁存电路，并将该信号作为触发器的输出输出。 第一移位方向信号通过第一开关提供给锁存电路，第二移位方向信号通过第二开关提供给锁存电路。 在除了第一级和最后级之外的每个单元电路中，来自前一级的输出信号被提供给第一开关的控制端，并且来自后级的输出信号被提供给第二开关的控制端 。
-
19.发明授权公开(公告)号：US08971478B2
公开(公告)日：2015-03-03
申请号：US13575490
申请日：2011-02-10
CPC分类号： G11C19/28 , G09G3/3677
摘要： A shift register includes a plurality of stages of unit circuits each including a flip-flop. Each of the unit circuits generates, by obtaining a sync signal in accordance with an output from the flip-flop, an output signal. The flip-flop includes a first switch and a second switch and a latch circuit for latching a signal supplied thereto and outputting the signal as the output from the flip-flop. A first shift direction signal is supplied to the latch circuit via the first switch, and the second shift direction signal is supplied to the latch circuit via the second switch. In each unit circuit other than those of the first and last stages, an output signal from a previous stage is supplied to a control terminal of the first switch, and an output signal from a subsequent stage is supplied to a control terminal of the second switch.
摘要翻译： 移位寄存器包括多个阶段的单元电路，每个单元电路包括一个触发器。 每个单元电路通过根据触发器的输出获得同步信号来产生输出信号。 触发器包括第一开关和第二开关以及用于锁存提供给其的信号的锁存电路，并将该信号作为触发器的输出输出。 第一移位方向信号通过第一开关提供给锁存电路，第二移位方向信号通过第二开关提供给锁存电路。 在除了第一级和最后级之外的每个单元电路中，来自前一级的输出信号被提供给第一开关的控制端，并且来自后级的输出信号被提供给第二开关的控制端 。
-
公开(公告)号：US20120200614A1
公开(公告)日：2012-08-09
申请号：US13501368
申请日：2010-06-02
CPC分类号： G09G3/3614 , G09G3/3655 , G09G3/3674 , G09G3/3677 , G09G2300/0876 , G09G2310/0264 , G09G2310/0286 , G09G2310/08 , G09G2320/0219 , G09G2320/0233 , G09G2340/0407
摘要： In a display device (i) which carries out a display based on a video signal whose resolution has been converted to higher resolution (high-resolution conversion driving) and (ii) which carries out CC driving, when the resolution of the video signal is converted by a factor of 2 (double-size display), assuming that a direction in which the gate lines extend is a row-wise direction, signal potentials having the same polarity and the same gray scale are supplied to pixel electrodes included in respective two pixels that correspond to two adjacent gate lines and that are adjacent to each other in the column-wise direction (scanning direction), and a direction of change in the signal potentials written to the pixel electrodes from the source lines varies every two adjacent rows according to the polarities of the signal potentials.
摘要翻译： 在基于分辨率被转换为更高分辨率（高分辨率转换驱动）的视频信号和执行CC驱动的（ii））执行显示的显示装置（i）中，当视频信号的分辨率为 转换为2倍（双倍尺寸显示），假设栅极线延伸的方向是行方向，具有相同极性和相同灰度的信号电位被提供给包括在相应两个中的像素电极 对应于两个相邻的栅极线并且在列方向（扫描方向）上彼此相邻的像素，并且从源极线写入像素电极的信号电位的变化方向根据 到信号电位的极性。
-
-
-
-
-
-
-
-
-
搜索结果
65 条记录 (耗时 0.027 秒)
