公开(公告)号：US20050212060A1

公开(公告)日：2005-09-29

申请号：US11108698

申请日：2005-04-19

申请人： Kazumi Nishinohara

发明人： Kazumi Nishinohara

IPC分类号： H01L29/786 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/6659 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/6656

摘要： There is disclosed a semiconductor device which comprises a semiconductor substrate, a pair of element isolating insulating films separately formed in the semiconductor substrate and defining an element region, a pair of impurity diffusion regions formed in the element regions and in contact with the element isolating insulating films, respectively, a channel region interposed between the pair of impurity diffusion regions, and a gate electrode formed via a gate insulating film on the channel region, the gate electrode being disposed away from end portions of the impurity diffusion regions. The gate length of the gate electrode is limited to 30 nm or less, the distance between the impurity diffusion regions and the edges of the gate electrode is respectively limited to 10 nm or less, and the distribution in lateral direction of impurity concentration in the impurity diffusion regions is limited to 1 digit/3 nm or more.

摘要翻译： 公开了一种半导体器件，其包括半导体衬底，分别形成在半导体衬底中并限定元件区域的一对元件隔离绝缘膜，形成在元件区域中并与元件隔离绝缘体接触的一对杂质扩散区域 分别设置在一对杂质扩散区域之间的沟道区域，以及通过沟道区域上的栅极绝缘膜形成的栅电极，栅电极远离杂质扩散区域的端部。 栅电极的栅极长度限制在30nm以下，杂质扩散区域与栅电极的边缘之间的距离分别限制在10nm以下，杂质浓度在横向上的杂质分布 扩散区域限制在1位数/ 3nm以上。

公开(公告)号：US06770944B2

公开(公告)日：2004-08-03

申请号：US10303806

申请日：2002-11-26

申请人： Kazumi Nishinohara ,  Yasushi Akasaka ,  Kyoichi Suguro

发明人： Kazumi Nishinohara ,  Yasushi Akasaka ,  Kyoichi Suguro

IPC分类号： H01L2976

CPC分类号： H01L29/66583 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/105 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66628

摘要： A semiconductor device has a first semiconductor region formed in a semiconductor substrate and having a first conductivity type due to first-conductivity-type active impurities contained in the first semiconductor region, and a second semiconductor region formed between the first semiconductor region and the surface of the semiconductor substrate and having a second conductivity type due to second-conductivity-type active impurities contained in the second semiconductor region. The second semiconductor region contains first-conductivity-type active impurities whose concentration is zero or smaller than a quarter of a concentration of the second-conductivity-type active impurities contained in the second semiconductor region. An insulating film and a conductor are formed on the second semiconductor region. Third and fourth semiconductor regions of the second conductivity type are formed at the semiconductor surface in contact with the side faces of the second semiconductor region. This semiconductor device is capable of suppressing net impurity concentration variations as well as threshold voltage variations to be caused by a short channel effect or manufacturing variations.

摘要翻译： 半导体器件具有形成在半导体衬底中并且由于第一半导体区域中包含的第一导电型有源杂质而具有第一导电类型的第一半导体区域，以及形成在第一半导体区域和第一半导体区域之间的第二半导体区域 并且由于第二半导体区域中包含的第二导电型有源杂质而具有第二导电类型。 第二半导体区域包含浓度为零或小于第二半导体区域中所含的第二导电型有源杂质的浓度的四分之一的第一导电型活性杂质。 绝缘膜和导体形成在第二半导体区域上。 在与第二半导体区域的侧面接触的半导体表面处形成第二导电类型的第三和第四半导体区域。 该半导体器件能够抑制净杂质浓度变化以及由短沟道效应或制造变化引起的阈值电压变化。

公开(公告)号：US06465842B2

公开(公告)日：2002-10-15

申请号：US09344105

申请日：1999-06-24

申请人： Kazumi Nishinohara

发明人： Kazumi Nishinohara

IPC分类号： H01L2976

CPC分类号： H01L29/66621 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7834

摘要： A MIS type semiconductor device comprises a semiconductor layer provided with a recess portion having a side wall with an obtuse angle at least at a portion of the recess portion, a gate electrode formed over a bottom surface of the recess portion, with a gate insulating film interposed, a source region and a drain region formed on sides of the gate electrode with an insulating film interposed, such that boundary planes between the source region and the drain region, on one hand, and the insulating film, on the other hand, are formed in the semiconductor layer at an angle to a surface of the semiconductor layer, and wiring portions for contact with the surface of the semiconductor layer. Wherein an edge of the gate electrode is located inside the recess portion provided in the semiconductor layer, and there is provided at least one of a mutually opposed portion between the gate electrode and the source region and a mutually opposed portion between the gate electrode and the drain region, whereby at least one of a portion of the source region and a portion of the drain region, which lie in the associated mutually opposed portions, functions as an accumulation layer.

摘要翻译： MIS型半导体器件包括半导体层，该半导体层设置有至少在凹部的一部分处具有钝角的侧壁的凹部，形成在凹部的底面的栅电极，栅极绝缘膜 插入有形成在栅电极的侧面上的源极区域和漏极区域，绝缘膜插入，另一方面，源极区域和漏极区域之间的边界面以及绝缘膜是 在半导体层中以与半导体层的表面成一定角度的方式形成，以及用于与半导体层的表面接触的布线部分。 其中栅电极的边缘位于设置在半导体层中的凹部内部，并且在栅电极和源极区之间设置相互相对的部分中的至少一个以及栅电极和栅电极之间的相互对置的部分 漏极区域，由此位于相关联的相对部分中的源极区域的一部分和漏极区域的一部分中的至少一个用作累积层。

公开(公告)号：US07349750B2

公开(公告)日：2008-03-25

申请号：US11480373

申请日：2006-07-05

申请人： Kazumi Nishinohara ,  Mitsutoshi Nakamura ,  Kyoichi Suguro ,  Koji Shirai ,  Ichiro Taguchi

发明人： Kazumi Nishinohara ,  Mitsutoshi Nakamura ,  Kyoichi Suguro ,  Koji Shirai ,  Ichiro Taguchi

IPC分类号： G06F19/00

CPC分类号： G05B19/41885 ,  G05B2219/45031 ,  Y02P90/20 ,  Y02P90/26

摘要： A method for optimizing a structure of an industrial product includes selecting control factors from among manufacturing parameters affecting a target characteristic, which is scheduled to be manufactured by a sequence of manufacturing processes; setting levels to the respective control factors; selecting a reference characteristic having a trade-off relation with the target characteristic from among characteristics of the structure; setting a reference value to the reference characteristic; selecting a prior adjustment factor affecting the reference characteristic; creating conditions for experiments assigning combinations of the levels to the respective control factors; determining an adjustment value of the prior adjustment factor so that each of characteristic values of the reference characteristic obtained by the experiments conforms substantially to the reference value; and determining experimental characteristic values of the target characteristic using the adjustment value.

公开(公告)号：US5162880A

公开(公告)日：1992-11-10

申请号：US589436

申请日：1990-09-27

申请人： Hiroaki Hazama ,  Kazumi Nishinohara

发明人： Hiroaki Hazama ,  Kazumi Nishinohara

IPC分类号： H01L27/115 ,  H01L29/861

CPC分类号： H01L29/8616 ,  H01L27/115

摘要： A nonvolatile memory cell comprises a semiconductor substrate of first conduction type, a high-concentration impurity region of second conduction type formed on the semiconductor substrate and connected to a bit line, an insulation film in which carrier traps are formed, and a gate electrode that is opposite the high-concentration impurity region across the insulation film and connected to a word line. Carriers are captured by, and released from, the carrier traps formed in the insulation film, in response to bias voltages applied to the word and bit lines. Information stored in the memory cell depends on whether or not the carrier traps are holding carriers. The information is read out of the memory cell as the difference of a tunneling current flowing between the semiconductor substrate and the high-concentration impurity region.

摘要翻译： 非易失性存储单元包括：第一导电类型的半导体衬底，形成在半导体衬底上并连接到位线的第二导电类型的高浓度杂质区域，其中形成载流子阱的绝缘膜;以及栅电极， 与绝缘膜上的高浓度杂质区相对并连接到字线。 响应于施加到字和位线的偏置电压，承载体被捕获并从其中形成的载流子捕集阱释放。 存储在存储器单元中的信息取决于载波陷阱是否是保持载波。 该信息作为在半导体衬底和高浓度杂质区域之间流动的隧道电流的差异从存储单元中读出。

公开(公告)号：US20080140229A1

公开(公告)日：2008-06-12

申请号：US12007723

申请日：2008-01-15

申请人： Kazumi Nishinohara ,  Mitsutoshi Nakamura ,  Kyoichi Suguro ,  Koji Shirai ,  Ichiro Taguchi

发明人： Kazumi Nishinohara ,  Mitsutoshi Nakamura ,  Kyoichi Suguro ,  Koji Shirai ,  Ichiro Taguchi

IPC分类号： G05B13/02

CPC分类号： G05B19/41885 ,  G05B2219/45031 ,  Y02P90/20 ,  Y02P90/26

摘要： A method for optimizing a structure of an industrial product includes selecting control factors from among manufacturing parameters affecting a target characteristic, which is scheduled to be manufactured by a sequence of manufacturing processes; setting levels to the respective control factors; selecting a reference characteristic having a trade-off relation with the target characteristic from among characteristics of the structure; setting a reference value to the reference characteristic; selecting a prior adjustment factor affecting the reference characteristic; creating conditions for experiments assigning combinations of the levels to the respective control factors; determining an adjustment value of the prior adjustment factor so that each of characteristic values of the reference characteristic obtained by the experiments conforms substantially to the reference value; and determining experimental characteristic values of the target characteristic using the adjustment value.

摘要翻译： 一种用于优化工业产品结构的方法包括从影响目标特性的制造参数中选择控制因子，该目标特性被安排由一系列制造过程制造; 设定各个控制因素的水平; 从结构的特征中选择具有与目标特性的权衡关系的参考特征; 将参考值设置为参考特性; 选择影响参考特征的先前调整因子; 创建将各级的组合分配给各个控制因素的实验条件; 确定现有调整因子的调整值，使得通过实验获得的参考特性的每个特征值基本上符合参考值; 以及使用所述调整值来确定所述目标特性的实验特性值。

公开(公告)号：US06911705B2

公开(公告)日：2005-06-28

申请号：US10677289

申请日：2003-10-03

申请人： Kazumi Nishinohara

发明人： Kazumi Nishinohara

IPC分类号： H01L29/786 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/6659 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/6656

摘要： There is disclosed a semiconductor device which comprises a semiconductor substrate, a pair of element isolating insulating films separately formed in the semiconductor substrate and defining an element region, a pair of impurity diffusion regions formed in the element regions and in contact with the element isolating insulating films, respectively, a channel region interposed between the pair of impurity diffusion regions, and a gate electrode formed via a gate insulating film on the channel region, the gate electrode being disposed away from end portions of the impurity diffusion regions. The gate length of the gate electrode is limited to 30 nm or less, the distance between the impurity diffusion regions and the edges of the gate electrode is respectively limited to 10 nm or less, and the distribution in lateral direction of impurity concentration in the impurity diffusion regions is limited to 1 digit/3 nm or more.

摘要翻译： 公开了一种半导体器件，其包括半导体衬底，分别形成在半导体衬底中并限定元件区域的一对元件隔离绝缘膜，形成在元件区域中并与元件隔离绝缘体接触的一对杂质扩散区域 分别设置在一对杂质扩散区域之间的沟道区域，以及通过沟道区域上的栅极绝缘膜形成的栅电极，栅电极远离杂质扩散区域的端部。 栅电极的栅极长度限制在30nm以下，杂质扩散区域与栅电极的边缘之间的距离分别限制在10nm以下，杂质浓度在横向上的杂质分布 扩散区域限制在1位数/ 3nm以上。

公开(公告)号：US20050077570A1

公开(公告)日：2005-04-14

申请号：US10942032

申请日：2004-09-16

申请人： Kazumi Nishinohara

发明人： Kazumi Nishinohara

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/66621 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7834

摘要： A MIS type semiconductor device comprises a semiconductor layer provided with a recess portion having a side wall with an obtuse angle at least at a portion of the recess portion, a gate electrode formed over a bottom surface of the recess portion, with a gate insulating film interposed, a source region and a drain region formed on sides of the gate electrode with an insulating film interposed, such that boundary planes between the source region and the drain region, on one hand, and the insulating film, on the other hand, are formed in the semiconductor layer at an angle to a surface of the semiconductor layer, and wiring portions for contact with the surface of the semiconductor layer. Wherein an edge of the gate electrode is located inside the recess portion provided in the semiconductor layer, and there is provided at least one of a mutually opposed portion between the gate electrode and the source region and a mutually opposed portion between the gate electrode and the drain region, whereby at least one of a portion of the source region and a portion of the drain region, which lie in the associated mutually opposed portions, functions as an accumulation layer.

摘要翻译： MIS型半导体器件包括半导体层，该半导体层设置有至少在凹部的一部分处具有钝角的侧壁的凹部，形成在凹部的底面的栅电极，栅极绝缘膜 插入有形成在栅电极的侧面上的源极区域和漏极区域，绝缘膜插入，另一方面，源极区域和漏极区域之间的边界面以及绝缘膜是 在半导体层中以与半导体层的表面成一定角度的方式形成，以及用于与半导体层的表面接触的布线部分。 其中栅电极的边缘位于设置在半导体层中的凹部内部，并且在栅电极和源极区之间设置相互相对的部分中的至少一个以及栅电极和栅电极之间的相互对置的部分 漏极区域，由此位于相关联的相对部分中的源极区域的一部分和漏极区域的一部分中的至少一个用作累积层。

公开(公告)号：US20050023567A1

公开(公告)日：2005-02-03

申请号：US10677289

申请日：2003-10-03

申请人： Kazumi Nishinohara

发明人： Kazumi Nishinohara

IPC分类号： H01L29/786 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/10

CPC分类号： H01L29/6659 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/6656

摘要： There is disclosed a semiconductor device which comprises a semiconductor substrate, a pair of element isolating insulating films separately formed in the semiconductor substrate and defining an element region, a pair of impurity diffusion regions formed in the element regions and in contact with the element isolating insulating films, respectively, a channel region interposed between the pair of impurity diffusion regions, and a gate electrode formed via a gate insulating film on the channel region, the gate electrode being disposed away from end portions of the impurity diffusion regions. The gate length of the gate electrode is limited to 30 nm or less, the distance between the impurity diffusion regions and the edges of the gate electrode is respectively limited to 10 nm or less, and the distribution in lateral direction of impurity concentration in the impurity diffusion regions is limited to 1 digit/3 nm or more.