公开(公告)号：US06541829B2

公开(公告)日：2003-04-01

申请号：US09726486

申请日：2000-12-01

申请人： Kazumi Nishinohara ,  Yasushi Akasaka ,  Kyoichi Suguro

发明人： Kazumi Nishinohara ,  Yasushi Akasaka ,  Kyoichi Suguro

IPC分类号： H01L2976

CPC分类号： H01L29/66583 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/105 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66628

摘要： A semiconductor device has a first semiconductor region formed in a semiconductor substrate and having a first conductivity type due to first-conductivity-type active impurities contained in the first semiconductor region, and a second semiconductor region formed between the first semiconductor region and the surface of the semiconductor substrate and having a second conductivity type due to second-conductivity-type active impurities contained in the second semiconductor region. The second semiconductor region contains first-conductivity-type active impurities whose concentration is zero or smaller than a quarter of a concentration of the second-conductivity-type active impurities contained in the second semiconductor region. An insulating film and a conductor are formed on the second semiconductor region. Third and fourth semiconductor regions of the second conductivity type are formed at the semiconductor surface in contact with the side faces of the second semiconductor region. This semiconductor device is capable of suppressing net impurity concentration variations as well as threshold voltage variations to be caused by a short channel effect or manufacturing variations.

公开(公告)号：US07078776B2

公开(公告)日：2006-07-18

申请号：US10867797

申请日：2004-06-16

申请人： Kazumi Nishinohara ,  Yasushi Akasaka ,  Kyoichi Suguro

发明人： Kazumi Nishinohara ,  Yasushi Akasaka ,  Kyoichi Suguro

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/66583 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/105 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66628

摘要： A semiconductor device has a first semiconductor region formed in a semiconductor substrate and having a first conductivity type due to first-conductivity-type active impurities contained in the first semiconductor region, and a second semiconductor region formed between the first semiconductor region and the surface of the semiconductor substrate and having a second conductivity type due to second-conductivity-type active impurities contained in the second semiconductor region. The second semiconductor region contains first-conductivity-type active impurities, whose concentration is zero or smaller than a quarter of a concentration of the second-conductivity-type active impurities contained in the second semiconductor region. An insulating film and a conductor are formed on the second semiconductor region. Third and fourth semiconductor regions of the second conductivity type are formed at the semiconductor surface in contact with the side faces of the second semiconductor region. This semiconductor device is capable of suppressing net impurity concentration variations as well as threshold voltage variations to be caused by a short channel effect or manufacturing variations.

摘要翻译： 半导体器件具有形成在半导体衬底中并且由于第一半导体区域中包含的第一导电型有源杂质而具有第一导电类型的第一半导体区域，以及形成在第一半导体区域和第一半导体区域之间的第二半导体区域 并且由于第二半导体区域中包含的第二导电型有源杂质而具有第二导电类型。 第二半导体区域包含第一导电型有源杂质，其浓度为零或小于第二半导体区域中所含的第二导电型有源杂质浓度的四分之一。 绝缘膜和导体形成在第二半导体区域上。 在与第二半导体区域的侧面接触的半导体表面处形成第二导电类型的第三和第四半导体区域。 该半导体器件能够抑制净杂质浓度变化以及由短沟道效应或制造变化引起的阈值电压变化。

公开(公告)号：US06770944B2

公开(公告)日：2004-08-03

申请号：US10303806

申请日：2002-11-26

申请人： Kazumi Nishinohara ,  Yasushi Akasaka ,  Kyoichi Suguro

发明人： Kazumi Nishinohara ,  Yasushi Akasaka ,  Kyoichi Suguro

IPC分类号： H01L2976

CPC分类号： H01L29/66583 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/105 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66628

摘要： A semiconductor device has a first semiconductor region formed in a semiconductor substrate and having a first conductivity type due to first-conductivity-type active impurities contained in the first semiconductor region, and a second semiconductor region formed between the first semiconductor region and the surface of the semiconductor substrate and having a second conductivity type due to second-conductivity-type active impurities contained in the second semiconductor region. The second semiconductor region contains first-conductivity-type active impurities whose concentration is zero or smaller than a quarter of a concentration of the second-conductivity-type active impurities contained in the second semiconductor region. An insulating film and a conductor are formed on the second semiconductor region. Third and fourth semiconductor regions of the second conductivity type are formed at the semiconductor surface in contact with the side faces of the second semiconductor region. This semiconductor device is capable of suppressing net impurity concentration variations as well as threshold voltage variations to be caused by a short channel effect or manufacturing variations.

摘要翻译： 半导体器件具有形成在半导体衬底中并且由于第一半导体区域中包含的第一导电型有源杂质而具有第一导电类型的第一半导体区域，以及形成在第一半导体区域和第一半导体区域之间的第二半导体区域 并且由于第二半导体区域中包含的第二导电型有源杂质而具有第二导电类型。 第二半导体区域包含浓度为零或小于第二半导体区域中所含的第二导电型有源杂质的浓度的四分之一的第一导电型活性杂质。 绝缘膜和导体形成在第二半导体区域上。 在与第二半导体区域的侧面接触的半导体表面处形成第二导电类型的第三和第四半导体区域。 该半导体器件能够抑制净杂质浓度变化以及由短沟道效应或制造变化引起的阈值电压变化。

公开(公告)号：US07584011B2

公开(公告)日：2009-09-01

申请号：US12007723

申请日：2008-01-15

申请人： Kazumi Nishinohara ,  Mitsutoshi Nakamura ,  Kyoichi Suguro ,  Koji Shirai ,  Ichiro Taguchi

发明人： Kazumi Nishinohara ,  Mitsutoshi Nakamura ,  Kyoichi Suguro ,  Koji Shirai ,  Ichiro Taguchi

IPC分类号： G06F19/00

CPC分类号： G05B19/41885 ,  G05B2219/45031 ,  Y02P90/20 ,  Y02P90/26

摘要： A method for optimizing a structure of an industrial product includes selecting control factors from among manufacturing parameters affecting a target characteristic, which is scheduled to be manufactured by a sequence of manufacturing processes; setting levels to the respective control factors; selecting a reference characteristic having a trade-off relation with the target characteristic from among characteristics of the structure; setting a reference value to the reference characteristic; selecting a prior adjustment factor affecting the reference characteristic; creating conditions for experiments assigning combinations of the levels to the respective control factors; determining an adjustment value of the prior adjustment factor so that each of characteristic values of the reference characteristic obtained by the experiments conforms substantially to the reference value; and determining experimental characteristic values of the target characteristic using the adjustment value.

摘要翻译： 一种用于优化工业产品结构的方法包括从影响目标特性的制造参数中选择控制因子，该目标特性被安排由一系列制造过程制造; 设定各个控制因素的水平; 从结构的特征中选择具有与目标特性的权衡关系的参考特征; 将参考值设置为参考特性; 选择影响参考特征的先前调整因子; 创建将各级的组合分配给各个控制因素的实验条件; 确定现有调整因子的调整值，使得通过实验获得的参考特性的每个特征值基本上符合参考值; 以及使用所述调整值来确定所述目标特性的实验特性值。

公开(公告)号：US20070067056A1

公开(公告)日：2007-03-22

申请号：US11480373

申请日：2006-07-05

申请人： Kazumi Nishinohara ,  Mitsutoshi Nakamura ,  Kyoichi Suguro ,  Koji Shirai ,  Ichiro Taguchi

发明人： Kazumi Nishinohara ,  Mitsutoshi Nakamura ,  Kyoichi Suguro ,  Koji Shirai ,  Ichiro Taguchi

IPC分类号： G06F19/00

CPC分类号： G05B19/41885 ,  G05B2219/45031 ,  Y02P90/20 ,  Y02P90/26

摘要： A method for optimizing a structure of an industrial product includes selecting control factors from among manufacturing parameters affecting a target characteristic, which is scheduled to be manufactured by a sequence of manufacturing processes; setting levels to the respective control factors; selecting a reference characteristic having a trade-off relation with the target characteristic from among characteristics of the structure; setting a reference value to the reference characteristic; selecting a prior adjustment factor affecting the reference characteristic; creating conditions for experiments assigning combinations of the levels to the respective control factors; determining an adjustment value of the prior adjustment factor so that each of characteristic values of the reference characteristic obtained by the experiments conforms substantially to the reference value; and determining experimental characteristic values of the target characteristic using the adjustment value.

摘要翻译： 一种用于优化工业产品结构的方法包括从影响目标特性的制造参数中选择控制因子，该目标特性被安排由一系列制造过程制造; 设定各个控制因素的水平; 从结构的特征中选择具有与目标特性的权衡关系的参考特征; 将参考值设置为参考特性; 选择影响参考特征的先前调整因子; 创建将各级的组合分配给各个控制因素的实验条件; 确定现有调整因子的调整值，使得通过实验获得的参考特性的每个特征值基本上符合参考值; 以及使用所述调整值来确定所述目标特性的实验特性值。

公开(公告)号：US07349750B2

公开(公告)日：2008-03-25

申请号：US11480373

申请日：2006-07-05

申请人： Kazumi Nishinohara ,  Mitsutoshi Nakamura ,  Kyoichi Suguro ,  Koji Shirai ,  Ichiro Taguchi

发明人： Kazumi Nishinohara ,  Mitsutoshi Nakamura ,  Kyoichi Suguro ,  Koji Shirai ,  Ichiro Taguchi

IPC分类号： G06F19/00

CPC分类号： G05B19/41885 ,  G05B2219/45031 ,  Y02P90/20 ,  Y02P90/26

摘要： A method for optimizing a structure of an industrial product includes selecting control factors from among manufacturing parameters affecting a target characteristic, which is scheduled to be manufactured by a sequence of manufacturing processes; setting levels to the respective control factors; selecting a reference characteristic having a trade-off relation with the target characteristic from among characteristics of the structure; setting a reference value to the reference characteristic; selecting a prior adjustment factor affecting the reference characteristic; creating conditions for experiments assigning combinations of the levels to the respective control factors; determining an adjustment value of the prior adjustment factor so that each of characteristic values of the reference characteristic obtained by the experiments conforms substantially to the reference value; and determining experimental characteristic values of the target characteristic using the adjustment value.

公开(公告)号：US20080140229A1

公开(公告)日：2008-06-12

申请号：US12007723

申请日：2008-01-15

申请人： Kazumi Nishinohara ,  Mitsutoshi Nakamura ,  Kyoichi Suguro ,  Koji Shirai ,  Ichiro Taguchi

发明人： Kazumi Nishinohara ,  Mitsutoshi Nakamura ,  Kyoichi Suguro ,  Koji Shirai ,  Ichiro Taguchi

IPC分类号： G05B13/02

CPC分类号： G05B19/41885 ,  G05B2219/45031 ,  Y02P90/20 ,  Y02P90/26

摘要： A method for optimizing a structure of an industrial product includes selecting control factors from among manufacturing parameters affecting a target characteristic, which is scheduled to be manufactured by a sequence of manufacturing processes; setting levels to the respective control factors; selecting a reference characteristic having a trade-off relation with the target characteristic from among characteristics of the structure; setting a reference value to the reference characteristic; selecting a prior adjustment factor affecting the reference characteristic; creating conditions for experiments assigning combinations of the levels to the respective control factors; determining an adjustment value of the prior adjustment factor so that each of characteristic values of the reference characteristic obtained by the experiments conforms substantially to the reference value; and determining experimental characteristic values of the target characteristic using the adjustment value.

摘要翻译： 一种用于优化工业产品结构的方法包括从影响目标特性的制造参数中选择控制因子，该目标特性被安排由一系列制造过程制造; 设定各个控制因素的水平; 从结构的特征中选择具有与目标特性的权衡关系的参考特征; 将参考值设置为参考特性; 选择影响参考特征的先前调整因子; 创建将各级的组合分配给各个控制因素的实验条件; 确定现有调整因子的调整值，使得通过实验获得的参考特性的每个特征值基本上符合参考值; 以及使用所述调整值来确定所述目标特性的实验特性值。

公开(公告)号：US06939787B2

公开(公告)日：2005-09-06

申请号：US10962504

申请日：2004-10-13

申请人： Fumio Ohtake ,  Yasushi Akasaka ,  Atsushi Murakoshi ,  Kyoichi Suguro

发明人： Fumio Ohtake ,  Yasushi Akasaka ,  Atsushi Murakoshi ,  Kyoichi Suguro

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L29/49 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/6656 ,  H01L21/28061 ,  H01L21/28247 ,  H01L29/4941

摘要： The semiconductor device comprises a pair of impurity diffused regions formed in a silicon substrate 10, spaced from each other, and a gate electrode 26 formed above the silicon substrate 10 between the pair of impurity diffused regions 38 intervening a gate insulation film 12 therebetween. The gate electrode 26 is formed of a polycrystalline silicon film 16 formed on the gate insulation film 12, a polycrystalline silicon film 30 formed on the polycrystalline silicon film 16 and having crystal grain boundaries discontinuous to the polycrystalline silicon film 16, a metal nitride film 20 formed on the polycrystalline silicon film 30, and a metal film 22 formed on the barrier metal film 20. Whereby diffusion of the boron from the first polycrystalline silicon film 16 toward the metal nitride film 20 can be decreased. Thus, depletion of the gate electrode 26 can be suppressed.

摘要翻译： 半导体器件包括彼此间隔开的形成在硅衬底10中的一对杂质扩散区域，以及在栅极绝缘膜12之间形成的一对杂质扩散区域38之间形成在硅衬底10上方的栅电极26。 栅电极26由形成在栅极绝缘膜12上的多晶硅膜16，形成在多晶硅膜16上并具有与多晶硅膜16不连续的晶粒边界的多晶硅膜30，金属氮化物膜20 形成在多晶硅膜30上，金属膜22形成在阻挡金属膜20上。 由此可以减少硼从第一多晶硅膜16朝向金属氮化物膜20的扩散。 因此，能够抑制栅电极26的耗尽。

公开(公告)号：US5903053A

公开(公告)日：1999-05-11

申请号：US677397

申请日：1996-07-09

申请人： Tadashi Iijima ,  Hisako Ono ,  Kyoichi Suguro ,  Yasushi Akasaka ,  Shinichi Nakamura

发明人： Tadashi Iijima ,  Hisako Ono ,  Kyoichi Suguro ,  Yasushi Akasaka ,  Shinichi Nakamura

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L23/52 ,  H01L29/45 ,  H01L29/49 ,  H01L29/78 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L29/4975 ,  H01L29/45 ,  H01L29/4933 ,  H01L29/4941 ,  H01L29/495 ,  H01L29/7833 ,  H01L2924/0002

摘要： A semiconductor device comprising a conductive layer and an amorphous alloy layer formed on the bottom surface of said conductive layer and acting as a barrier layer. The conductive layer is either an electrode layer or a wiring layer. The amorphous alloy layer is made of a matrix phase and microcrystal grains. The matrix phase consists mainly of a Ti--Si--N amorphous alloy. The microcrystal grains are dispersed in the matrix phase, not continuously arranged in the direction of thickness of the amorphous alloy layer.

摘要翻译： 一种半导体器件，包括形成在所述导电层的底表面上并用作阻挡层的导电层和非晶态合金层。 导电层是电极层或布线层。 非晶合金层由基体相和微晶粒构成。 基体相主要由Ti-Si-N非晶合金组成。 微晶粒分散在基体相中，不是沿非晶合金层的厚度方向连续排列。

公开(公告)号：US07772671B2

公开(公告)日：2010-08-10

申请号：US12068635

申请日：2008-02-08

申请人： Kyoichi Suguro ,  Kiyotaka Miyano ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Takayuki Hiraoka ,  Yasushi Akasaka ,  Tsunetoshi Arikado

发明人： Kyoichi Suguro ,  Kiyotaka Miyano ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Takayuki Hiraoka ,  Yasushi Akasaka ,  Tsunetoshi Arikado

IPC分类号： H01L29/00

CPC分类号： H01L21/28194 ,  H01L21/28088 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/76262 ,  H01L21/823481 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66537 ,  H01L29/66545

摘要： A semiconductor device including a semiconductor substrate having on its surface a recess and at least one projection formed in the recess. The projection has a channel region and an element isolating insulating film is formed in the recess. A MIS type semiconductor element is formed on the semiconductor substrate and includes a gate electrode formed on the channel region of the projection via a gate insulating film. Source and drain regions are formed to pinch the channel region of the projection therebetween. A channel region of the MIS type semiconductor element is formed to reach the at least one projection located adjacent to the MIS type semiconductor element in its channel width direction via the recess. A top surface of the at least one projection is located higher than the top surface of the element isolating insulating film by 20 nm or more.

摘要翻译： 一种半导体器件，包括在其表面上具有凹部的半导体衬底和形成在凹部中的至少一个突起。 突起具有沟道区域，并且在凹部中形成元件隔离绝缘膜。 MIS半导体元件形成在半导体衬底上，并且包括通过栅极绝缘膜形成在突起的沟道区上的栅电极。 形成源区和漏区以夹住其间的突起的沟道区。 MIS型半导体元件的沟道区域形成为经由凹部在其沟道宽度方向上到达位于与MIS型半导体元件相邻的至少一个突起。 所述至少一个突起的顶表面比所述元件隔离绝缘膜的顶表面高20nm或更大。