公开(公告)号：US20130076434A1

公开(公告)日：2013-03-28

申请号：US13243880

申请日：2011-09-23

Applicant: Zaw Soe

Inventor： Zaw Soe

IPC: H03B1/00 ,  H03F3/45

CPC classification number: H03H11/1217 ,  H03F3/195 ,  H03F3/301 ,  H03F3/45179 ,  H03F3/505 ,  H03F2203/45528 ,  H03F2203/45544 ,  H03F2203/45594 ,  H03H3/00

Abstract: A Sallen-Key filter requires an operational amplifier with a large input impedance and a small output impedance to meet the external filter characteristics. The operational amplifier requires an internal feedback path for stability that limits performance. This invention eliminates the need for internal feedback and increases the gain of a source follower which has characteristics matching the operational amplifier in the Sallen-Key filter. The source follower provides 6 dB of AC voltage gain and is substituted for the operational amplifier in the Sallen-Key filter. The Sallen-Key filter requires a differential configuration to generate all the required signals with their compliments and uses these signals in a feed forward path. Furthermore, since the source follower uses only two n-channel stacked devices, the headroom voltage is maximized to several hundred millivolts for a 1.2V voltage supply in a 40 nm CMOS technology. Thus, the required 880 MHz bandwidth of the Sallen-Key filter can be easily met using the innovative source follower.

Abstract translation: Sallen-Key滤波器需要具有大输入阻抗和小输出阻抗的运算放大器，以满足外部滤波器特性。 运算放大器需要一个内部反馈路径来稳定性，从而限制性能。 本发明消除了对内部反馈的需要，并且增加了具有与Sallen-Key滤波器中的运算放大器匹配的特性的源极跟随器的增益。 源极跟随器提供6 dB的交流电压增益，并代替Sallen-Key滤波器中的运算放大器。 Sallen-Key滤波器需要差分配置，以产生所有需要的信号，并在前馈路径中使用这些信号。 此外，由于源极跟随器仅使用两个n沟道堆叠器件，因此在40nm CMOS技术中，1.2V电压源的裕量电压最大可达数百毫伏。 因此，Sallen-Key滤波器所需的880 MHz带宽可以使用创新的源跟踪器轻松实现。

公开(公告)号：US20070155348A1

公开(公告)日：2007-07-05

申请号：US11321348

申请日：2005-12-29

Applicant: Behzad Razavi ,  Zaw Soe

Inventor： Behzad Razavi ,  Zaw Soe

IPC: H04B1/04

CPC classification number: H04B1/719 ,  H04B1/71635

Abstract: The present invention describes a transmitter/receiver architecture that uses a Weaver architecture in conjunction with digitally controlled adder/subtractor components to insert/extract a signal into/from the multi-channel system. In the transmitter, the selection of the band select bit causes the up/downconverted IF baseband I and Q signals to insert/extract on either side of an RF LO signal. In addition, the image of the first LO is eliminated while the desired signal is enhanced after passing through this new architecture. The invention also adds an RSSI circuit to the MBOA Weaver architecture receiver architecture to detect whether an 802.11 WLAN signal is interfering with the desired UWB signal. If so, the system is designed to detect this interference and jump to a new frequency range to avoid this interference. This invention focuses on devices that operate over the entire UWB band including the newly formed 60 GHz UWB band system.

Abstract translation: 本发明描述了一种使用Weaver架构结合数字控制的加法器/减法器组件来将信号插入/从多通道系统中提取的发射机/接收机体系结构。 在发射机中，频带选择位的选择会导致上/下转换的IF基带I和Q信号在RF LO信号的任一侧插入/提取。 另外，消除了第一个LO的图像，同时在通过这个新架构之后增强了所需的信号。 本发明还向MBOA Weaver架构接收机架构添加了RSSI电路，以检测802.11 WLAN信号是否干扰所需的UWB信号。 如果是这样，系统被设计为检测这种干扰并跳转到新的频率范围以避免这种干扰。 本发明专注于在包括新形成的60GHz UWB频带系统的整个UWB频带上工作的设备。

公开(公告)号：US20050258989A1

公开(公告)日：2005-11-24

申请号：US10851307

申请日：2004-05-21

Applicant: Kuangyu Li ,  Song-Nien Tang ,  Jackie Cheng ,  Zaw Soe

Inventor： Kuangyu Li ,  Song-Nien Tang ,  Jackie Cheng ,  Zaw Soe

IPC: H03M1/06 ,  H03M1/10 ,  H03M1/18

CPC classification number: H03M1/1019 ,  H03M1/18

Abstract: Systems and methods for canceling static and dynamic DC offsets by combining a digital DC offset correction scheme with an analog DC offset correction scheme. A feedback-based digital DC offset correction scheme provides different adjustment levels for a plurality of discrete gain states and the analog DC offset correction scheme operates in different cancellation modes dependent on a frame structure. A digital DC offset correction scheme collects DC offset control information and provides adjustment levels. In addition, a negative-feedback based switchable high pass filter has a plurality modes of operation, where one mode of operation includes an all-pass filter.

Abstract translation: 通过组合数字直流偏移校正方案和模拟直流偏移校正方案来消除静态和动态直流偏移的系统和方法。 基于反馈的数字DC偏移校正方案为多个离散增益状态提供不同的调整电平，并且模拟DC偏移校正方案根据帧结构在不同的取消模式下操作。 数字DC偏移校正方案收集直流偏移控制信息并提供调整电平。 此外，基于负反馈的可切换高通滤波器具有多种操作模式，其中一种操作模式包括全通滤波器。

公开(公告)号：US08626106B2

公开(公告)日：2014-01-07

申请号：US13312806

申请日：2011-12-06

Applicant: Zaw Soe

Inventor： Zaw Soe

IPC: H04B1/16 ,  H03F3/19

CPC classification number: H03F1/42 ,  H03D7/125 ,  H03D7/1441 ,  H03D7/1466 ,  H03D7/165 ,  H03F1/223 ,  H03F3/193 ,  H03F3/387 ,  H03F3/45071 ,  H03F3/45179 ,  H03F2200/108 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2200/492 ,  H03F2200/72 ,  H03F2200/75 ,  H04L27/38

Abstract: A cascode common source and common gate LNAs operating at 60 GHz are introduced and described. The cascode common source LNA is simulated to arrive at an optimum ratio of upper device width to the lower device width. The voltage output of the cascode common source LNA is translated into a current to feed and apply energy to the mixer stage. These input current signals apply the energy associated with the current directly into the switched capacitors in the mixer to minimize the overall power dissipation of the system. The LNA is capacitively coupled to the mixer switches in the I and Q mixers and are enabled and disabled by the clocks generated by the quadrature oscillator. These signals are then amplified by a differential amplifier to generate the sum and difference frequency spectra.

Abstract translation: 引入并描述了以60GHz操作的共源共栅和公共栅极LNA。 对共源共栅源LNA进行模拟，以达到上部器件宽度与较低器件宽度的最佳比例。 共源共栅源LNA的电压输出转换为电流以馈送并将能量施加到混频器级。 这些输入电流信号将与电流相关联的能量直接施加到混频器中的开关电容器中，以最小化系统的总功耗。 LNA电容耦合到I和Q混频器中的混频器开关，并由正交振荡器产生的时钟使能和禁止。 然后，这些信号被差分放大器放大以产生和和差频谱。

公开(公告)号：US20130076408A1

公开(公告)日：2013-03-28

申请号：US13243908

申请日：2011-09-23

Applicant: Zaw Soe

Inventor： Zaw Soe

IPC: H03B19/00 ,  H03F3/45

CPC classification number: H03K21/023 ,  H03L7/193

Abstract: A phase lock loop (PLL) is an important component in wireless systems. CMOS technology offers voltage controlled oscillator designs operating at 60 GHz. One of the difficulties is dividing the high frequency clock down to a manageable clock frequency using conventional CMOS. Although injection locked dividers can divide down this clock frequency, these dividers have limitations. A divide by 2 is presented that uses several techniques; feed forward, clock amplification and series peaked inductors to overcome these limitations.

Abstract translation: 锁相环（PLL）是无线系统中的重要组成部分。 CMOS技术提供工作在60 GHz的压控振荡器设计。 其中一个困难是使用传统的CMOS将高频时钟降低到可管理的时钟频率。 虽然注入锁定分频器可以分频此时钟频率，但这些分频器有局限性。 提出了使用几种技术的除以2; 前馈，时钟放大和串联峰值电感，以克服这些局限性。

公开(公告)号：US08406710B1

公开(公告)日：2013-03-26

申请号：US13243986

申请日：2011-09-23

Applicant: Zaw Soe

Inventor： Zaw Soe

IPC: H01Q11/12 ,  H04K3/00

CPC classification number: H01Q11/12

Abstract: Very high frequency circuits suffer from parasitic resistances. At 60 GHz, conventional layout techniques can introduce loss into the circuit at critical locations. One critical interconnect between the output of a pre-driver and the gate of the final output stage causes 1 or 2 dB of loss due to the layout. By minimizing the number of via contacts, this conventional loss can be recovered using this new layout technique. In addition, a tap point of a via stack is used to modify the resonant characteristics of the interconnect. Finally, cross coupled devices in a resonant circuit are used to reduce the common mode noise at the expense of the common mode gain.

Abstract translation: 超高频电路遭受寄生电阻。 在60GHz，传统的布局技术可以在关键位置引入电路损耗。 预驱动器的输出和最终输出级的栅极之间的一个关键互连会导致由于布局导致1或2 dB的损耗。 通过最小化通孔触点的数量，可以使用这种新的布局技术来恢复传统的损耗。 此外，使用通孔堆叠的抽头点来修改互连的谐振特性。 最后，谐振电路中的交叉耦合器件用于以共模增益为代价来降低共模噪声。

公开(公告)号：US20070236267A1

公开(公告)日：2007-10-11

申请号：US11398278

申请日：2006-04-05

Applicant: Behzad Razavi ,  Zaw Soe

Inventor： Behzad Razavi ,  Zaw Soe

IPC: H03K3/00

CPC classification number: H03K3/012 ,  H03K3/356043

Abstract: The inventive technique can dynamically adjust the current being applied within the components of a prescaler or divider. This dynamic scaling of the current can improve the speed of the divider by a factor of two or reduce the average current in half when compared to the conventional prescaler. Inverters are used to directly adjust the dynamic value of the currents. The removal of the conventional NMOS device within the conventional circuit eliminates one gate delay in the CML prescaler. Second, the inventive prescaler circuits operate under a current injection/extraction technique. A group of small matched inverters can be used to drive each current switching circuit independently within the entire prescaler as compared to a large buffer driving the entire conventional prescaler. Finally, dynamic current scaling offers the designer additional flexibility in the design trade off between the maximum current applied to the load and achieving the maximum performance.

Abstract translation: 本发明的技术可以动态地调节在预分频器或分频器的组件内施加的电流。 电流的这种动态缩放可以将分频器的速度提高一倍，或者将传统的预分频器的平均电流减小一半。 逆变器用于直接调整电流的动态值。 常规电路中的常规NMOS器件的去除消除了CML预分频器中的一个门延迟。 第二，本发明的预分频器电路在当前的注入/提取技术下工作。 与驱动整个常规预分频器的大型缓冲器相比，一组小型匹配的反相器可以在整个预分频器内单独驱动每个电流开关电路。 最后，动态电流扩展为设计人员提供了额外的灵活性，可以在施加到负载的最大电流和实现最大性能之间进行折衷。

公开(公告)号：US20070218851A1

公开(公告)日：2007-09-20

申请号：US11804516

申请日：2007-05-16

Applicant: Zaw Soe ,  Tony Yang ,  Jackie Cheng ,  Sining Zhou ,  Kuangyu Li ,  Fei-Ran Yang ,  Shoufang Chen ,  Tom Baker

Inventor： Zaw Soe ,  Tony Yang ,  Jackie Cheng ,  Sining Zhou ,  Kuangyu Li ,  Fei-Ran Yang ,  Shoufang Chen ,  Tom Baker

IPC: H04B1/16

CPC classification number: H04B1/403

Abstract: Multistage RF transmitter and receiver circuits may use independently variable RF and IF local oscillators, allowing the RF and IF local oscillator frequencies for a given RF channel to be selected to have a large common factor with respect to the reference oscillator used by the local oscillator circuits, thus allowing the use of small divisor numbers in the local oscillator circuits and reducing phase noise. Independent high-side and low-side RF local oscillators may be provided and selectively used depending on the RF channel to be transmitted or received.

公开(公告)号：US20050264335A1

公开(公告)日：2005-12-01

申请号：US10856075

申请日：2004-05-28

Applicant: Zaw Soe

Inventor： Zaw Soe

IPC: H03H11/26

CPC classification number: H03H11/265

Abstract: Delays are produced in differential signals using a variable capacitance provided by MOS varactors coupled between the differential signals. The capacitance values of the MOS varactors is controlled by a bias voltage applied to the bodies of the varactors. Selective application of bias voltages to the MOS varactors may be employed to selectively delay one pair of differential signals with respect to another pair of differential signals so as to change the relative phases of the signals. A logic circuit may be used to control the application of bias voltage to the MOS varactors so that signal phases may be adjusted in a manner that is predictable and programmable. These methods may be implemented to compensate for phase offsets between in-phase and quadrature signals of a local oscillator.

Abstract translation: 使用由差分信号之间耦合的MOS变容二极管提供的可变电容在差分信号中产生延迟。 MOS可变电抗器的电容值由施加到变容二极体的偏置电压来控制。 可以选择性地施加偏置电压到MOS可变电抗器，以便相对于另一对差分信号选择性地延迟一对差分信号，以便改变信号的相对相位。 可以使用逻辑电路来控制向MOS可变电抗器施加偏置电压，使得可以以可预测和可编程的方式调整信号相位。 可以实现这些方法来补偿本地振荡器的同相和正交信号之间的相位偏移。