公开(公告)号：US08643119B2

公开(公告)日：2014-02-04

申请号：US12182212

申请日：2008-07-30

申请人： Zhijiong Luo ,  Huilong Zhu ,  Yung Fu Chong ,  Hung Y. Ng ,  Kern Rim ,  Nivo Rovedo

发明人： Zhijiong Luo ,  Huilong Zhu ,  Yung Fu Chong ,  Hung Y. Ng ,  Kern Rim ,  Nivo Rovedo

IPC分类号： H01L29/76

CPC分类号： H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure for a semiconductor device, according to an embodiment, includes: a substantially L-shaped silicide element including a base member and an extended member, wherein the base member extends at least partially into a shallow trench isolation (STI) region such that a substantially horizontal surface of the base member directly contacts a substantially horizontal surface of the STI region; and a contact contacting the substantially L-shaped silicide element.

摘要翻译： 根据实施例的用于半导体器件的结构包括：基本上L形的硅化物元件，其包括基底构件和延伸构件，其中所述基底构件至少部分地延伸到浅沟槽隔离（STI）区域中，使得 基部构件的基本水平的表面直接接触STI区域的基本水平的表面; 以及接触基本上L形的硅化物元件的接触。

公开(公告)号：US20070269952A1

公开(公告)日：2007-11-22

申请号：US11383952

申请日：2006-05-17

申请人： Yung Fu Chong ,  Kevin K. Dezfulian ,  Zhijiong Luo ,  Huilong Zhu

发明人： Yung Fu Chong ,  Kevin K. Dezfulian ,  Zhijiong Luo ,  Huilong Zhu

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/3065 ,  H01L21/31116 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636

摘要： The present invention relates to semiconductor integrated circuits. More particularly, but not exclusively, the invention relates to strained channel complimentary metal oxide semiconductor (CMOS) transistor structures and fabrication methods thereof. There is provided a method of forming a strained channel transistor structure on a substrate, comprising the steps of: forming a source stressor recess comprising a deep source recess and a source extension recess; forming a drain stressor recess comprising a deep drain recess and a drain extension recess; and subsequently forming a source stressor in said source stressor recess and a drain stressor in said drain stressor recess. The deep source/drain and source/drain extension stressors are formed by an uninterrupted etch process and an uninterrupted epitaxy process.

摘要翻译： 本发明涉及半导体集成电路。 更具体地但非唯一地，本发明涉及应变通道互补金属氧化物半导体（CMOS）晶体管结构及其制造方法。 提供了一种在衬底上形成应变通道晶体管结构的方法，包括以下步骤：形成包括深源凹槽和源极延伸凹槽的源极应力器凹部; 形成包括深排水凹槽和排水延伸凹槽的排水应力槽; 并且随后在所述源应力器凹部中形成源应力器，以及在所述漏应力器凹部中形成漏应力器。 深源/漏极和源极/漏极延伸应力源通过不间断的蚀刻工艺和不间断的外延工艺形成。

公开(公告)号：US20070293016A1

公开(公告)日：2007-12-20

申请号：US11424076

申请日：2006-06-14

申请人： Zhijiong Luo ,  Hung Y. Ng ,  Nivo Rovedo ,  Phung T. Nguyen ,  William C. Wille ,  Richard Lindsay ,  Zhao Lun ,  Yung Fu Chong ,  Siddhartha Panda

发明人： Zhijiong Luo ,  Hung Y. Ng ,  Nivo Rovedo ,  Phung T. Nguyen ,  William C. Wille ,  Richard Lindsay ,  Zhao Lun ,  Yung Fu Chong ,  Siddhartha Panda

IPC分类号： H01L21/76

CPC分类号： H01L21/823892 ,  H01L21/76218 ,  H01L21/76232 ,  H01L21/823878

摘要： A semiconductor structure includes a base semiconductor substrate having a doped region located therein, and an epitaxial region located over the doped region. The semiconductor structure also includes a final isolation region located with the doped region and the epitaxial region. The final isolation region has a greater linewidth within the doped region than within the epitaxial region. A method for fabricating the semiconductor structure provides for forming the doped region prior to the epitaxial region. The doped region may be formed with reduced well implant energy and reduced lateral straggle. The final isolation region with the variable linewidth provides a greater effective isolation depth than an actual trench isolation depth.

摘要翻译： 半导体结构包括具有位于其中的掺杂区的基极半导体衬底和位于掺杂区上方的外延区。 半导体结构还包括位于掺杂区和外延区的最后隔离区。 最后的隔离区域在掺杂区域内具有比外延区域内更大的线宽。 制造半导体结构的方法提供了在外延区之前形成掺杂区。 掺杂区域可以形成为具有减少的良好注入能量和减小的横向分层。 具有可变线宽的最终隔离区域提供比实际沟槽隔离深度更大的有效隔离深度。

公开(公告)号：US08288825B2

公开(公告)日：2012-10-16

申请号：US12780962

申请日：2010-05-17

申请人： Yung Fu Chong ,  Zhijiong Luo ,  Joo Chan Kim ,  Judson Robert Holt

发明人： Yung Fu Chong ,  Zhijiong Luo ,  Joo Chan Kim ,  Judson Robert Holt

IPC分类号： H01L21/70

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636

摘要： A structure and method for forming raised source/drain structures in a NFET device and embedded SiGe source/drains in a PFET device. We provide a NFET gate structure over a NFET region in a substrate and PFET gate structure over a PFET region. We provide NFET SDE regions adjacent to the NFET gate and provide PFET SDE regions adjacent to the PFET gate. We form recesses in the PFET region in the substrate adjacent to the PFET second spacers. We form a PFET embedded source/drain stressor in the recesses. We form a NFET S/D epitaxial Si layer over the NFET SDE regions and a PFET S/D epitaxial Si layer over PFET embedded source/drain stressor. The epitaxial Si layer over PFET embedded source/drain stressor is consumed in a subsequent salicide step to form a stable and low resistivity silicide over the PFET embedded source/drain stressor. We perform a NFET S/D implant by implanting N-type ions into NFET region adjacent to the NFET gate structure and into the NFET S/D stressor Si layer to form the raised NFET source/drains.

摘要翻译： 用于在NFET器件中形成凸起的源极/漏极结构并在PFET器件中形成嵌入的SiGe源极/漏极的结构和方法。 我们在衬底上的NFET区域和PFET区域上的PFET栅极结构提供NFET栅极结构。 我们提供与NFET栅极相邻的NFET SDE区域，并提供与PFET栅极相邻的PFET SDE区域。 我们在邻近PFET第二间隔物的衬底中的PFET区域中形成凹陷。 我们在凹槽中形成PFET嵌入式源极/漏极应力器。 我们在NFET SDE区域上形成NFET S / D外延Si层，并在PFET嵌入式源极/漏极应力器上形成PFET S / D外延Si层。 在随后的自对准硅化物步骤中，在PFET嵌入式源极/漏极应力源上的外延Si层被消耗，以在PFET嵌入式源极/漏极应力器上形成稳定和低电阻率的硅化物。 我们通过将N型离子注入到与NFET栅极结构相邻的NFET区域中并进入NFET S / D应力Si层来形成NFET S / D注入，以形成升高的NFET源极/漏极。

公开(公告)号：US07972921B2

公开(公告)日：2011-07-05

申请号：US11369239

申请日：2006-03-06

申请人： Yung Fu Chong ,  Zhijiong Luo

发明人： Yung Fu Chong ,  Zhijiong Luo

IPC分类号： H01L21/8238

CPC分类号： H01L21/76232 ,  H01L21/823481

摘要： A method of manufacturing a self-aligned inverted T-shaped isolation structure. An integrated circuit isolation system including providing a substrate, forming a base insulator region in the substrate, growing the substrate to surround the base insulator region, and depositing an insulator column having a narrower width than the base insulator region on the base insulator region.

摘要翻译： 一种制造自对准的倒T形隔离结构的方法。 一种集成电路隔离系统，包括提供衬底，在所述衬底中形成基极绝缘体区域，使所述衬底生长以围绕所述基极绝缘体区域，以及沉积具有比所述基极绝缘体区域上的所述基底绝缘体区域窄的宽度的绝缘体柱。

公开(公告)号：US20100320503A1

公开(公告)日：2010-12-23

申请号：US12852995

申请日：2010-08-09

申请人： Yung Fu Chong ,  Zhijiong Luo ,  Judson Holt

发明人： Yung Fu Chong ,  Zhijiong Luo ,  Judson Holt

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66628 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636

摘要： The present invention relates to semiconductor integrated circuits. More particularly, but not exclusively, the invention relates to strained channel complimentary metal oxide semiconductor (CMOS) transistor structures and fabrication methods thereof. A strained channel CMOS transistor structure comprises a source stressor region comprising a source extension stressor region; and a drain stressor region comprising a drain extension stressor region; wherein a strained channel region is formed between the source extension stressor region and the drain extension stressor region, a width of said channel region being defined by adjacent ends of said extension stressor regions.

摘要翻译： 本发明涉及半导体集成电路。 更具体地但非唯一地，本发明涉及应变通道互补金属氧化物半导体（CMOS）晶体管结构及其制造方法。 应变通道CMOS晶体管结构包括源应力源区域，其包括源延伸应力区域; 和漏极应力区域，包括漏极延伸应力区域; 其中在所述源延伸应力区域和所述漏极延伸应力区域之间形成应变通道区域，所述沟道区域的宽度由所述延伸应力区域的相邻端限定。

公开(公告)号：US20080023752A1

公开(公告)日：2008-01-31

申请号：US11460766

申请日：2006-07-28

申请人： Xiangdong Chen ,  Yung Fu Chong ,  Zhijiong Luo ,  Xinlin Wang ,  Haining S. Yang

发明人： Xiangdong Chen ,  Yung Fu Chong ,  Zhijiong Luo ,  Xinlin Wang ,  Haining S. Yang

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L21/26586 ,  H01L29/1045 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636

摘要： An n-type field effect transistor (NFET) and methods of forming a halo for an NFET to control the short channel effect are disclosed. One method includes forming a gate over a silicon substrate; recessing the silicon adjacent to the gate; forming a halo by epitaxially growing boron in-situ doped silicon germanium (SiGe) in the recess; and epitaxially growing silicon over the silicon germanium. Alternatively, the halo can be formed by ion implanting boron into an embedded SiGe region within the silicon substrate. The resulting NFET includes a boron doped SiGe halo embedded within the silicon substrate. The embedded SiGe layer may be a relaxed layer without inserting strain in the channel. The high solid solubility of boron in SiGe and low diffusion rate allows formation of a halo that will maintain the sharp profile, which provides better control of the short channel effect and increasing control over NFET threshold voltage roll-off.

摘要翻译： 公开了一种n型场效应晶体管（NFET）和用于形成用于NFET的光晕以控制短沟道效应的方法。 一种方法包括在硅衬底上形成栅极; 凹陷与栅极相邻的硅; 通过在凹槽中外延生长硼原位掺杂硅锗（SiGe）来形成卤素; 并在硅锗上外延生长硅。 或者，可以通过将硼离子注入到硅衬底内的嵌入的SiGe区域中来形成卤素。 所得NFET包括嵌入在硅衬底内的硼掺杂SiGe光晕。 嵌入的SiGe层可以是松弛层，而不会在通道中插入应变。 硼在SiGe中的高固体溶解度和低扩散速率允许形成将保持尖锐轮廓的光晕，这提供了对短通道效应的更好控制并增加了对NFET阈值电压滚降的控制。

公开(公告)号：US08450775B2

公开(公告)日：2013-05-28

申请号：US13229773

申请日：2011-09-12

申请人： Yung Fu Chong ,  Zhijiong Luo ,  Judson Robert Holt

发明人： Yung Fu Chong ,  Zhijiong Luo ,  Judson Robert Holt

IPC分类号： H01L21/02

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： An example embodiment of a strained channel transistor structure comprises the following: a strained channel region comprising a first semiconductor material with a first natural lattice constant; a gate dielectric layer overlying the strained channel region; a gate electrode overlying the gate dielectric layer; and a source region and drain region oppositely adjacent to the strained channel region, one or both of the source region and drain region are comprised of a stressor region comprised of a second semiconductor material with a second natural lattice constant different from the first natural lattice constant; the stressor region has a graded concentration of a dopant impurity and/or of a stress inducing molecule. Another example embodiment is a process to form the graded impurity or stress inducing molecule stressor embedded S/D region, whereby the location/profile of the S/D stressor is not defined by the recess depth/profile.

摘要翻译： 应变通道晶体管结构的示例性实施例包括以下：包含具有第一自然晶格常数的第一半导体材料的应变通道区域; 覆盖在应变通道区上的栅介质层; 覆盖所述栅介质层的栅电极; 以及源极区域和漏极区域，其与所述应变通道区域相邻地邻近，所述源极区域和漏极区域中的一个或两个由包含第二半导体材料的应力区域构成，所述第二半导体材料具有不同于所述第一自然晶格常数的第二自然晶格常数 ; 应力区域具有掺杂剂杂质和/或应力诱导分子的分级浓度。 另一个示例性实施例是形成渐变杂质或应力诱导分子应力嵌入S / D区域的过程，由此S / D应力器的位置/轮廓不由凹槽深度/轮廓限定。

公开(公告)号：US07718500B2

公开(公告)日：2010-05-18

申请号：US11305584

申请日：2005-12-16

申请人： Yung Fu Chong ,  Zhijiong Luo ,  Joo Chan Kim ,  Judson Robert Holt

发明人： Yung Fu Chong ,  Zhijiong Luo ,  Joo Chan Kim ,  Judson Robert Holt

IPC分类号： H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636

摘要： A structure and method for forming raised source/drain structures in a NFET device and embedded SiGe source/drains in a PFET device. We provide a NFET gate structure over a NFET region in a substrate and PFET gate structure over a PFET region. We provide NFET SDE regions adjacent to the NFET gate and provide PFET SDE regions adjacent to the PFET gate. We form recesses in the PFET region in the substrate adjacent to the PFET second spacers. We form a PFET embedded source/drain stressor in the recesses. We form a NFET S/D epitaxial Si layer over the NFET SDE regions and a PFET S/D epitaxial Si layer over PFET embedded source/drain stressor. The epitaxial Si layer over PFET embedded source/drain stressor is consumed in a subsequent salicide step to form a stable and low resistivity silicide over the PFET embedded source/drain stressor. We perform a NFET S/D implant by implanting N-type ions into NFET region adjacent to the NFET gate structure and into the NFET S/D stressor Si layer to form the raised NFET source/drains.

摘要翻译： 用于在NFET器件中形成凸起的源极/漏极结构并在PFET器件中形成嵌入的SiGe源极/漏极的结构和方法。 我们在衬底上的NFET区域和PFET区域上的PFET栅极结构提供NFET栅极结构。 我们提供与NFET栅极相邻的NFET SDE区域，并提供与PFET栅极相邻的PFET SDE区域。 我们在邻近PFET第二间隔物的衬底中的PFET区域中形成凹陷。 我们在凹槽中形成PFET嵌入式源极/漏极应力器。 我们在NFET SDE区域上形成NFET S / D外延Si层，并在PFET嵌入式源极/漏极应力器上形成PFET S / D外延Si层。 在随后的自对准硅化物步骤中，在PFET嵌入式源极/漏极应力源上的外延Si层被消耗，以在PFET嵌入式源极/漏极应力器上形成稳定和低电阻率的硅化物。 我们通过将N型离子注入到与NFET栅极结构相邻的NFET区域中并进入NFET S / D应力Si层来形成NFET S / D注入，以形成升高的NFET源极/漏极。

公开(公告)号：US08017487B2

公开(公告)日：2011-09-13

申请号：US11399016

申请日：2006-04-05

申请人： Yung Fu Chong ,  Zhijiong Luo ,  Judson Robert Holt

发明人： Yung Fu Chong ,  Zhijiong Luo ,  Judson Robert Holt

IPC分类号： H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A strained channel transistor structure and methods of forming a semiconductor device are presented. The transistor structure includes a strained channel region having a first semiconductor material with a first natural lattice constant. A gate dielectric layer overlying the strained channel region, a gate electrode overlying the gate dielectric layer and a source region and drain region oppositely adjacent to the strained channel region are provided. One or both of the source region and drain region include a stressor region having a second semiconductor material with a second natural lattice constant different from the first natural lattice constant. The stressor region has graded concentration of a dopant impurity and/or of a stress inducing molecule.

摘要翻译： 提出了应变通道晶体管结构和形成半导体器件的方法。 晶体管结构包括具有第一自然晶格常数的第一半导体材料的应变沟道区。 提供了覆盖应变通道区域的栅极电介质层，覆盖栅极电介质层的栅极电极和与应变通道区域相邻的源极区域和漏极区域。 源极区域和漏极区域中的一个或两个包括具有第二半导体材料的应力区域，其具有与第一自然晶格常数不同的第二自然晶格常数。 应激物区域具有掺杂剂杂质和/或应力诱导分子的渐变浓度。