公开(公告)号：US20070187748A1

公开(公告)日：2007-08-16

申请号：US11740698

申请日：2007-04-26

申请人： Chia-Shun Hsiao ,  Yi Ding

发明人： Chia-Shun Hsiao ,  Yi Ding

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11519 ,  H01L29/42328 ,  H01L29/66825

摘要： Dielectric regions (210) are formed on a semiconductor substrate between active areas of nonvolatile memory cells. The top portions of the dielectric region sidewalls are etched to recess the top portions laterally away from the active areas. Then a conductive layer is deposited to form the floating gates (410). The recessed portions of the dielectric sidewalls allow the floating gates to be wider at the top. The gate coupling ratio is increased as a result. Other features are also provided.

摘要翻译： 电介质区域（210）形成在非易失性存储单元的有源区域之间的半导体衬底上。 蚀刻电介质区域侧壁的顶部以将顶部部分横向远离有源区域。 然后沉积导电层以形成浮栅（410）。 电介质侧壁的凹陷部分允许浮动栅极在顶部较宽。 结果，门耦合比增大。 还提供其他功能。

公开(公告)号：US20070090409A1

公开(公告)日：2007-04-26

申请号：US11258119

申请日：2005-10-26

申请人： Chia-Shun Hsiao ,  Ming-Sheng Tung ,  Hong-Ming Chen ,  Ching-Hsien Huang

发明人： Chia-Shun Hsiao ,  Ming-Sheng Tung ,  Hong-Ming Chen ,  Ching-Hsien Huang

IPC分类号： H01L29/76 ,  H01L29/745

CPC分类号： H01L27/105 ,  H01L21/823456 ,  H01L27/1052

摘要： The present invention relates to a semiconductor device comprising at least one gate located in each of a memory array area and a periphery circuit area of a substrate, respectively, wherein the pattern density in the memory array area is higher than that in the periphery circuit area. The semiconductor device also comprises a barrier layer, which is located in the memory array area and the periphery circuit area, an undoped oxide barrier, which is located on the barrier layer in the periphery circuit area, and a boron-containing silicate glass, which is located on the barrier layer in the memory array area and on the undoped oxide barrier in the periphery circuit area.

摘要翻译： 本发明涉及一种半导体器件，其分别包括位于衬底的存储器阵列区域和外围电路区域中的至少一个栅极，其中存储器阵列区域中的图案密度高于外围电路区域中的图案密度 。 半导体器件还包括位于存储器阵列区域和外围电路区域中的阻挡层，位于外围电路区域中的阻挡层上的未掺杂的氧化物屏障和含硼硅酸盐玻璃，其中 位于存储器阵列区域中的阻挡层上和外围电路区域中未掺杂的氧化物屏障上。

公开(公告)号：US20060211255A1

公开(公告)日：2006-09-21

申请号：US11432222

申请日：2006-05-10

申请人： Chunchieh Huang ,  Chia-Shun Hsiao ,  Jin-Ho Kim ,  Kuei-Chang Tsai ,  Barbara Haselden ,  Daniel Wang

发明人： Chunchieh Huang ,  Chia-Shun Hsiao ,  Jin-Ho Kim ,  Kuei-Chang Tsai ,  Barbara Haselden ,  Daniel Wang

IPC分类号： H01L21/302

CPC分类号： H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11539

摘要： In integrated circuit fabrication, an etch is used that has a lateral component. For example, the etch may be isotropic. Before the isotropic etch of a layer (160), another etch of the same layer is performed. This other etch can be anisotropic. This etch attacks a portion (160X2) of the layer adjacent to the feature to be formed by the isotropic etch. That portion is entirely or partially removed by the anisotropic etch. Then the isotropic etch mask (420) is formed to extend beyond the feature over the location of the portion subjected to the anisotropic etch. If that portion was removed entirely, then the isotropic etch mask may completely seal off the feature to be formed on the side of that portion, so the lateral etching will not occur. If that portion was removed only partially, then the lateral undercut will be impeded because the passage to the feature under the isotropic etch mask will be narrowed.

摘要翻译： 在集成电路制造中，使用具有侧向分量的蚀刻。 例如，蚀刻可以是各向同性的。 在层（160）的各向同性蚀刻之前，执行相同层的另一蚀刻。 这种其他蚀刻可以是各向异性的。 该蚀刻攻击通过各向同性蚀刻形成的与特征相邻的层的部分（160×2）。 该部分被各向异性蚀刻完全或部分地去除。 然后，各向同性蚀刻掩模（420）被形成为延伸超过经过各向异性蚀刻的部分的位置的特征。 如果完全去除该部分，则各向同性蚀刻掩模可以完全密封要在该部分侧面上形成的特征，因此不会发生横向蚀刻。 如果该部分仅部分被去除，则横向底切将被阻碍，因为在各向同性蚀刻掩模下的特征的通过将变窄。

公开(公告)号：US20050133828A1

公开(公告)日：2005-06-23

申请号：US11048668

申请日：2005-01-31

申请人： Chia-Shun Hsiao ,  Dong Jun Kim

发明人： Chia-Shun Hsiao ,  Dong Jun Kim

IPC分类号： H01L21/311 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/423 ,  H01L27/148 ,  H01L21/76

CPC分类号： H01L21/76232 ,  H01L21/31111 ,  H01L21/823481 ,  H01L29/42368

摘要： A method and structure are provided with reduced gate wrap around to advantageously control for threshold voltage and increase stability in semiconductor devices. A spacer is provided aligned to field dielectric layers to protect the dielectric layers during subsequent etch processes. The spacer is then removed prior to subsequently forming a part of a gate oxide layer and a gate conductor layer. Advantageously, the spacer protects the corner area o the field dielectric and also allows for enhanced thickness of the gate oxide near the corners.

摘要翻译： 提供了一种方法和结构，其具有减少的栅极环绕，以有利地控制阈值电压并增加半导体器件的稳定性。 提供与场介电层对准的间隔物，以在随后的蚀刻工艺期间保护电介质层。 然后在随后形成栅极氧化物层和栅极导体层的一部分之前移除间隔物。 有利地，间隔物保护场电介质的角区域，并且还允许靠近拐角的栅极氧化物的增强的厚度。

公开(公告)号：US06399437B1

公开(公告)日：2002-06-04

申请号：US09099258

申请日：1998-06-18

申请人： Yung-Yi Hsu ,  Yi-Tsai Yi ,  Chia-Shun Hsiao ,  Ming-Huan Tsai

发明人： Yung-Yi Hsu ,  Yi-Tsai Yi ,  Chia-Shun Hsiao ,  Ming-Huan Tsai

IPC分类号： H01L218242

CPC分类号： H01L28/87 ,  H01L28/91

摘要： A method of forming a stacked capacitor having improved capacitance in a dynamic random access memory device is provided wherein and additional pad polysilicon layer is deposited prior to the forming of the capacitor cell contact area such that the side-wall of the capacitor cell can be increased. The increased side-wall thickness of the capacitor cell leads to an improved capacitance value for the cell. The present invention also provides a stacked capacitor formed in a semiconductor device that contains an additional pad polysilicon layer for increasing the thickness of the capacitor side-wall and subsequently its capacitance.

摘要翻译： 提供了一种在动态随机存取存储器件中形成具有改善的电容的叠层电容器的方法，其中在形成电容器单元接触区域之前淀积另外的焊盘多晶硅层，使得电容器单元的侧壁可以增加 。 电容器单元的增加的侧壁厚度导致电池的电容值改善。 本发明还提供一种形成在半导体器件中的堆叠电容器，其包含用于增加电容器侧壁的厚度和随后的电容的附加焊盘多晶硅层。

公开(公告)号：US20070093014A1

公开(公告)日：2007-04-26

申请号：US11258115

申请日：2005-10-26

申请人： Chia-Shun Hsiao ,  Ming-Sheng Tung ,  Hong-Ming Chen ,  Ching-Hsien Huang

发明人： Chia-Shun Hsiao ,  Ming-Sheng Tung ,  Hong-Ming Chen ,  Ching-Hsien Huang

IPC分类号： H01L21/8234 ,  H01L21/8238

CPC分类号： H01L27/105 ,  H01L21/823456 ,  H01L27/1052

摘要： The present invention provides a method for preventing doped boron in a dielectric layer from diffusing into a substrate. First, at least one gate is formed on a periphery circuit area and a memory array area of a substrate, respectively, wherein the pattern density in the memory array area is higher than that in the periphery circuit area. Then, a barrier layer is formed on the memory array area and the periphery circuit area, and an undoped oxide barrier is formed on the periphery circuit area. Finally, a silicate glass containing boron is deposited on the memory array area and the periphery circuit area.

摘要翻译： 本发明提供一种防止介电层中的掺杂硼扩散到衬底中的方法。 首先，分别在基板的外围电路区域和存储器阵列区域上形成至少一个栅极，其中存储器阵列区域中的图案密度高于外围电路区域中的图案密度。 然后，在存储器阵列区域和外围电路区域上形成阻挡层，并且在外围电路区域上形成未掺杂的氧化物屏障。 最后，将含硼的硅酸盐玻璃沉积在存储器阵列区域和外围电路区域上。

公开(公告)号：US07196381B2

公开(公告)日：2007-03-27

申请号：US11048668

申请日：2005-01-31

申请人： Chia-Shun Hsiao ,  Dong Jun Kim

发明人： Chia-Shun Hsiao ,  Dong Jun Kim

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/76232 ,  H01L21/31111 ,  H01L21/823481 ,  H01L29/42368

摘要： A method and structure are provided with reduced gate wrap around to advantageously control for threshold voltage and increase stability in semiconductor devices. A spacer is provided aligned to field dielectric layers to protect the dielectric layers during subsequent etch processes. The spacer is then removed prior to subsequently forming a part of a gate oxide layer and a gate conductor layer. Advantageously, the spacer protects the corner area o the field dielectric and also allows for enhanced thickness of the gate oxide near the corners.

摘要翻译： 提供了一种方法和结构，其具有减少的栅极环绕，以有利地控制阈值电压并增加半导体器件的稳定性。 提供与场介电层对准的间隔物，以在随后的蚀刻工艺期间保护电介质层。 然后在随后形成栅极氧化物层和栅极导体层的一部分之前移除间隔物。 有利地，间隔物保护场电介质的拐角区域并且还允许靠近拐角的栅极氧化物的增强的厚度。

公开(公告)号：US20050170646A1

公开(公告)日：2005-08-04

申请号：US10772932

申请日：2004-02-04

申请人： Chunchieh Huang ,  Chia-Shun Hsiao ,  Jin-Ho Kim ,  Kuei-Chang Tsai ,  Barbara Haselden ,  Daniel Wang

发明人： Chunchieh Huang ,  Chia-Shun Hsiao ,  Jin-Ho Kim ,  Kuei-Chang Tsai ,  Barbara Haselden ,  Daniel Wang

IPC分类号： H01L21/44 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115

CPC分类号： H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11539

摘要： In integrated circuit fabrication, an etch is used that has a lateral component. For example, the etch may be isotropic. Before the isotropic etch of a layer (160), another etch of the same layer is performed. This other etch can be anisotropic. This etch attacks a portion (160X2) of the layer adjacent to the feature to be formed by the isotropic etch. That portion is entirely or partially removed by the anisotropic etch. Then the isotropic etch mask (420) is formed to extend beyond the feature over the location of the portion subjected to the anisotropic etch. If that portion was removed entirely, then the isotropic etch mask may completely seal off the feature to be formed on the side of that portion, so the lateral etching will not occur. If that portion was removed only partially, then the lateral undercut will be impeded because the passage to the feature under the isotropic etch mask will be narrowed.

摘要翻译： 在集成电路制造中，使用具有侧向分量的蚀刻。 例如，蚀刻可以是各向同性的。 在层（160）的各向同性蚀刻之前，执行相同层的另一蚀刻。 这种其他蚀刻可以是各向异性的。 该蚀刻攻击通过各向同性蚀刻形成的与特征相邻的层的部分（160×2）。 该部分被各向异性蚀刻完全或部分地去除。 然后，各向同性蚀刻掩模（420）被形成为延伸超过经过各向异性蚀刻的部分的位置的特征。 如果完全去除该部分，则各向同性蚀刻掩模可以完全密封要在该部分侧面上形成的特征，因此不会发生横向蚀刻。 如果该部分仅部分被去除，则横向底切将被阻碍，因为在各向同性蚀刻掩模下的特征的通过将变窄。

公开(公告)号：US06821847B2

公开(公告)日：2004-11-23

申请号：US09969841

申请日：2001-10-02

申请人： Chung Wai Leung ,  Chia-Shun Hsiao ,  Vei-Han Chan

发明人： Chung Wai Leung ,  Chia-Shun Hsiao ,  Vei-Han Chan

IPC分类号： H01L218247

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： To fabricate a semiconductor memory, one or more pairs of first structures are formed over a semiconductor substrate. Each first structure comprises (a) a plurality of floating gates of memory cells and (b) a first conductive line providing control gates for the memory cells. The control gates overlie the floating gates. Each pair of the first structures corresponds to a plurality of doped regions each of which provides a source/drain region to a memory cell having the floating and control gates in one or the structure and a source/drain region to a memory cell having floating and control gates in the other one of the structures. For each pair, a second conductive line is formed whose bottom surface extends between the two structures and physically contacts the corresponding first doped regions. In some embodiments, the first doped regions are separated by insulation trenches. The second conductive line may form a conductive plug at least partially filling the region between the two first structures.

公开(公告)号：US06815760B2

公开(公告)日：2004-11-09

申请号：US10200443

申请日：2002-07-22

申请人： Chung Wai Leung ,  Chia-Shun Hsiao ,  Vei-Han Chan

发明人： Chung Wai Leung ,  Chia-Shun Hsiao ,  Vei-Han Chan

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： To fabricate a semiconductor memory, one or more pairs of first structures are formed over a semiconductor substrate. Each first structure comprises (a) a plurality of floating gates of memory cells and (b) a first conductive line providing control gates for the memory cells. The control gates overlie the floating gates. Each pair of the first structures corresponds to a plurality of doped regions each of which provides a source/drain region to a memory cell having the floating and control gates in one or the structure and a source/drain region to a memory cell having floating and control gates in the other one of the structures. For each pair, a second conductive line is formed whose bottom surface extends between the two structures and physically contacts the corresponding first doped regions. In some embodiments, the first doped regions are separated by insulation trenches. The second conductive line may form a conductive plug at least partially filling the region between the two first structures.