公开(公告)号：US20220418095A1

公开(公告)日：2022-12-29

申请号：US17396803

申请日：2021-08-09

Applicant: SFI ELECTRONICS TECHNOLOGY INC.

Inventor： CHING HOHN LIEN ,  HUNG TSUNG HSU ,  CHIH HSIEN HSU ,  CHENG HSIEN CHIU ,  HSING-TSAI HUANG

IPC: H05K1/02 ,  H05K9/00

Abstract: ESD suppressor and manufacturing method thereof. The ESD suppressor include at least two printed circuit boards, one insulating frame, two terminal electrodes and two or more interior electrodes. The insulating frame is positioned between the two printed circuit boards, so as to form a main structure with a cavity. For each printed circuit board, at least one interior electrode is positioned on the surface facing the cavity and separated from other interior electrode(s). Two terminal electrodes are positioned on two different surfaces of the main structure and electrically connected to different interior electrodes respectively. Optionally, the insulating frame is a hallowed out printed circuit board or a frame formed by printing insulating material. In the manufacturing method, the thickness of the insulating frame is adjusted to adjust the relative distance between different printed circuit boards, so as to further adjust the breakdown voltage of the ESD suppressor

公开(公告)号：US08488291B2

公开(公告)日：2013-07-16

申请号：US13023624

申请日：2011-02-09

Applicant: Ching-Hohn Lien ,  Jie-An Zhu ,  Zhi-Xian Xu ,  Xing-Xiang Huang ,  Ting-Yi Fang

Inventor： Ching-Hohn Lien ,  Jie-An Zhu ,  Zhi-Xian Xu ,  Xing-Xiang Huang ,  Ting-Yi Fang

IPC: H02H1/00

CPC classification number: H01C7/112 ,  H01C7/10 ,  H01C7/12

Abstract: A ZnO surge arrester for high-temperature operation is characterized in that a grain boundary layer between ZnO grains thereof contains a BaTiO3-based positive temperature coefficient thermistor material, which takes 10-85 mol % in the overall grain boundary layer, and when operating temperature raises, the positive temperature coefficient thermistor material in the grain boundary layer has its resistance sharply increasing with the raising temperature, so as to compensate or partially compensate decrease in resistance of components in the grain boundary layer caused by the raising temperature, thereby making the resistance of the grain boundary layer in the ZnO surge arrester more independent of temperature. The ZnO surge arrester thus is suitable for operation where a maximum operating temperature is higher than 125° C., or even higher than 150° C.

Abstract translation: 用于高温操作的ZnO避雷器的特征在于，其ZnO晶粒之间的晶界层包含基于BaTiO 3的正温度系数热敏电阻材料，其在整个晶界层中占据10-85mol％，并且当工作温度 升温时，晶界层中的正温度系数热敏电阻材料的电阻随着升温而急剧上升，从而补偿或部分补偿由升温引起的晶界层中的组分的电阻降低，从而使电阻 的ZnO避雷器中的晶界层更加独立于温度。 因此，ZnO避雷器适用于最高工作温度高于125℃或甚至高于150℃的操作。

公开(公告)号：US20120208040A1

公开(公告)日：2012-08-16

申请号：US13024470

申请日：2011-02-10

Applicant: Ching-Hohn LIEN ,  Hong-Zong Xu

Inventor： Ching-Hohn LIEN ,  Hong-Zong Xu

IPC: B32B15/02

CPC classification number: H01G4/005 ,  H01G4/30 ,  Y10T428/12056

Abstract: A multilayer ceramic device comprises a laminated ceramic body having opposite end surfaces, a pair of conductive electrodes each respectively attached to one end surface of the laminated ceramic body and a plurality of alternately staggered internal electrodes within the laminated ceramic body configured in an alternating manner and each electrically connected to the corresponding conductive electrodes respectively; each conductive electrodes of the multilayer ceramic device is further covered with a solder paste layer so that the multilayer ceramic device is thus made without any plating step and no need of treating waste liquid nickel or waste liquid tin as well as no problem of environmental pollution caused by plating solution, thereby lowering manufacturing costs and reducing processing time.

Abstract translation: 多层陶瓷器件包括具有相对端面的层叠陶瓷体，分别安装在层叠陶瓷体的一个端面上的一对导电电极和层叠陶瓷体内的多个交错交错的内部电极，其以交替的方式配置和 各自电连接到相应的导电电极; 多层陶瓷器件的每个导电电极进一步用焊膏层覆盖，使得多层陶瓷器件因此不经任何电镀步骤而制成，并且不需要处理废液镍或废液锡，并且没有引起环境污染的问题 通过电镀液，降低制造成本，缩短加工时间。

公开(公告)号：US07724124B2

公开(公告)日：2010-05-25

申请号：US11704987

申请日：2007-02-12

Applicant: Ching-Hohn Lien ,  Cheng-Tsung Kuo ,  Jun-Nun Lin ,  Jie-An Zhu ,  Li-Yun Zhang ,  Xing-Guang Huang ,  Wei-Cheng Lien

Inventor： Ching-Hohn Lien ,  Cheng-Tsung Kuo ,  Jun-Nun Lin ,  Jie-An Zhu ,  Li-Yun Zhang ,  Xing-Guang Huang ,  Wei-Cheng Lien

IPC: H01C7/10

CPC classification number: H01C7/105 ,  B82Y30/00 ,  C03C14/006 ,  C03C2214/05 ,  C03C2214/08 ,  C03C2214/16 ,  C04B35/453 ,  C04B35/46 ,  C04B35/4682 ,  C04B35/47 ,  C04B35/565 ,  C04B35/624 ,  C04B35/62805 ,  C04B35/62807 ,  C04B35/62886 ,  C04B2235/3275 ,  C04B2235/3284 ,  C04B2235/3298 ,  C04B2235/36 ,  C04B2235/405 ,  C04B2235/408 ,  C04B2235/5436 ,  C04B2235/5445 ,  C04B2235/5454 ,  C04B2235/6025 ,  H01C7/12

Abstract: A low-capacitance multilayer chip varistor has capacitance lower than 0.5 pF at 1 MHz and has a characteristic of resisting more than thousands of times of 8 KV electrostatic shock, which comprises a ceramic main body, outer electrodes disposed at two ends of the ceramic main body and inner electrodes disposed therein; the ceramic main body comprises inorganic glass of 3˜50 wt % and semi-conductive or conductive particles of 50˜97 wt % with particle size of more than 0.1 μm, and a layer of inorganic glass film covers the surface of semi-conductive or conductive particles, wherein the inorganic glass film contains semi-conductive or conductive particles of submicron or nanometer which is smaller than 1 micron, and the quantity contained of semi-conductive or conductive particles is less than 20 wt % of that of inorganic glass.

Abstract translation: 低容量多层片式压敏电阻在1MHz时的电容低于0.5pF，具有耐8千伏静电电击的数千倍的特性，其中包括一陶瓷主体，外电极位于陶瓷主体的两端 主体和内部电极; 陶瓷主体包含3〜50重量％的无机玻璃和粒径大于0.1μm的50〜97重量％的半导电性或导电性粒子，无机玻璃膜层覆盖半导电性或 导电颗粒，其中无机玻璃膜含有小于1微米的亚微米或纳米的半导电或导电颗粒，并且半导体或导电颗粒所含的量小于无机玻璃的20重量％。

公开(公告)号：US20100117271A1

公开(公告)日：2010-05-13

申请号：US12458369

申请日：2009-07-09

Applicant: Ching-Hohn Lien ,  Jie-An Zhu ,  Cheng-Tsung Kuo ,  Jiu-Nan Lin ,  Zhi-Xian Xu ,  Hong-Zong Xu ,  Ting-Yi Fang ,  Xing-Xiang Huang

Inventor： Ching-Hohn Lien ,  Jie-An Zhu ,  Cheng-Tsung Kuo ,  Jiu-Nan Lin ,  Zhi-Xian Xu ,  Hong-Zong Xu ,  Ting-Yi Fang ,  Xing-Xiang Huang

IPC: B28B1/00

CPC classification number: H01C7/112 ,  C04B35/453 ,  C04B2235/32 ,  C04B2235/3203 ,  C04B2235/3215 ,  C04B2235/3217 ,  C04B2235/3224 ,  C04B2235/3227 ,  C04B2235/3229 ,  C04B2235/3232 ,  C04B2235/3236 ,  C04B2235/3239 ,  C04B2235/3241 ,  C04B2235/3244 ,  C04B2235/3251 ,  C04B2235/3258 ,  C04B2235/3262 ,  C04B2235/3267 ,  C04B2235/3272 ,  C04B2235/3275 ,  C04B2235/3279 ,  C04B2235/3281 ,  C04B2235/3284 ,  C04B2235/3286 ,  C04B2235/3291 ,  C04B2235/3293 ,  C04B2235/3294 ,  C04B2235/3298 ,  C04B2235/3409 ,  C04B2235/3418 ,  C04B2235/36 ,  C04B2235/44 ,  C04B2235/442 ,  C04B2235/95

Abstract: A process for producing zinc oxide varistors is to perform the doping of zinc oxide and the sintering of zinc oxide grains with a high-impedance sintering material through two independent procedures, so that the doped zinc oxide and the high-impedance sintering material are well mixed in a predetermined ratio and then used to make the zinc oxide varistors through conventional technology by low-temperature sintering (lower than 900° C.); the resultant zinc oxide varistors may use pure silver as inner electrode and particularly possess one or more of varistor properties, thermistor properties, capacitor properties, inductor properties, piezoelectricity and magnetism.

Abstract translation: 一种生产氧化锌压敏电阻的方法是通过两个独立的步骤，用高阻抗烧结材料进行氧化锌的掺杂和氧化锌晶粒的烧结，使掺杂的氧化锌和高阻抗烧结材料充分混合 以预定的比例，然后通过低温烧结（低于900℃）通过常规技术制造氧化锌变阻器; 所得到的氧化锌变阻器可以使用纯银作为内部电极，特别是具有变阻器特性，热敏电阻特性，电容器特性，电感特性，压电性和磁性中的一种或多种。

公开(公告)号：US20210280373A1

公开(公告)日：2021-09-09

申请号：US16926324

申请日：2020-07-10

Applicant: SFI Electronics Technology Inc.

Inventor： Ching-Hohn Len ,  Hong Zong Xu ,  Zhi Xian Xu ,  Hsing Tsai Huang ,  Jie-An Zhu

IPC: H01G4/224 ,  H01G4/30

Abstract: An electrical device package structure and manufacturing method thereof is disclosed. The manufacturing method comprises: providing an electrical device body having at least two electrodes, wherein an outer surface of the electrical device body is partially covered by the electrodes, and outer surfaces of the electrodes are covered by a plastic material; forming a first protective layer including phosphate salt at least on the exposed outer surface of the electrical device body; and forming a second protective layer including glass at least on an exposed outer surface of the first protective layer. The present invention can prevent the electrical device body and/or the electrodes from being damaged on their manufacturing process, and avoid a forming high impedance layer on an electrode.

公开(公告)号：US20130011963A1

公开(公告)日：2013-01-10

申请号：US13614298

申请日：2012-09-13

Applicant: Ching-Hohn LIEN ,  Jie-An ZHU ,  Zhi-Xian XU ,  Hong-Zong XU ,  Ting-Yi FANG ,  Xing-Xiang HUANG

Inventor： Ching-Hohn LIEN ,  Jie-An ZHU ,  Zhi-Xian XU ,  Hong-Zong XU ,  Ting-Yi FANG ,  Xing-Xiang HUANG

IPC: H01L21/02

CPC classification number: C04B35/6261 ,  C01G9/02 ,  C01P2002/50 ,  C01P2002/52 ,  C01P2002/72 ,  C04B35/453 ,  C04B35/62645 ,  C04B35/64 ,  C04B2235/3203 ,  C04B2235/3217 ,  C04B2235/3224 ,  C04B2235/3225 ,  C04B2235/3227 ,  C04B2235/3229 ,  C04B2235/3232 ,  C04B2235/3239 ,  C04B2235/3241 ,  C04B2235/3244 ,  C04B2235/3251 ,  C04B2235/3258 ,  C04B2235/3267 ,  C04B2235/3272 ,  C04B2235/3274 ,  C04B2235/3275 ,  C04B2235/3279 ,  C04B2235/3281 ,  C04B2235/3284 ,  C04B2235/3286 ,  C04B2235/3291 ,  C04B2235/3293 ,  C04B2235/3294 ,  C04B2235/3298 ,  C04B2235/3409 ,  C04B2235/3418 ,  C04B2235/36 ,  C04B2235/42 ,  C04B2235/5454 ,  H01C7/112

Abstract: A process for producing zinc oxide varistors possessed a property of breakdown voltage (V1mA) ranging from 230 to 1,730 V/mm is to perform the doping of zinc oxide and the sintering of zinc oxide grains with a high-impedance sintered powder through two independent procedures, so that the doped zinc oxide and the high-impedance sintered powder are well mixed in a predetermined ratio and then used to make the zinc oxide varistors through conventional technology by low-temperature sintering (lower than 900° C.); the resultant zinc oxide varistors may use pure silver as inner electrode and particularly possess breakdown voltage ranging from 230 to 1,730 V/mm.

Abstract translation: 具有230〜1730V / mm的击穿电压（V1mA）的氧化锌变阻器的制造方法是通过两个独立的程序进行氧化锌的掺杂和氧化锌粒子与高阻抗烧结粉末的烧结 ，使得掺杂的氧化锌和高阻抗烧结粉末以预定比例充分混合，然后通过低温烧结（低于900℃）的常规技术制造氧化锌变阻器; 所得到的氧化锌变阻器可以使用纯银作为内部电极，特别是具有230至1730V / mm的击穿电压。

公开(公告)号：US20120057265A1

公开(公告)日：2012-03-08

申请号：US13023624

申请日：2011-02-09

Applicant: Ching-Hohn LIEN ,  Jie-An Zhu ,  Zhi-Xian Xu ,  Xing-Xiang Huang ,  Ting-Yi Fang

Inventor： Ching-Hohn LIEN ,  Jie-An Zhu ,  Zhi-Xian Xu ,  Xing-Xiang Huang ,  Ting-Yi Fang

IPC: H02H1/00

CPC classification number: H01C7/112 ,  H01C7/10 ,  H01C7/12

Abstract: A ZnO surge arrester for high-temperature operation is characterized in that a grain boundary layer between ZnO grains thereof contains a BaTiO3-based positive temperature coefficient thermistor material, which takes 10-85 mol % in the overall grain boundary layer, and when operating temperature raises, the positive temperature coefficient thermistor material in the grain boundary layer has its resistance sharply increasing with the raising temperature, so as to compensate or partially compensate decrease in resistance of components in the grain boundary layer caused by the raising temperature, thereby making the resistance of the grain boundary layer in the ZnO surge arrester more independent of temperature. The ZnO surge arrester thus is suitable for operation where a maximum operating temperature is higher than 125° C., or even higher than 150° C.

Abstract translation: 用于高温操作的ZnO避雷器的特征在于，其ZnO晶粒之间的晶界层包含基于BaTiO 3的正温度系数热敏电阻材料，其在整个晶界层中占据10-85mol％，并且当工作温度 升温时，晶界层中的正温度系数热敏电阻材料的电阻随着升温而急剧上升，从而补偿或部分补偿由升温引起的晶界层中的组分的电阻降低，从而使电阻 的ZnO避雷器中的晶界层更加独立于温度。 因此，ZnO避雷器适用于最高工作温度高于125℃或甚至高于150℃的操作。

公开(公告)号：US07541910B2

公开(公告)日：2009-06-02

申请号：US11440064

申请日：2006-05-25

Applicant: Wei-Cheng Lien ,  Cheng-Tsung Kuo ,  Jun-Nun Lin ,  Jie-An Zhu ,  Li-Yun Zhang

Inventor： Wei-Cheng Lien ,  Cheng-Tsung Kuo ,  Jun-Nun Lin ,  Jie-An Zhu ,  Li-Yun Zhang

IPC: H01C7/10

CPC classification number: H01C7/10 ,  H01C7/112 ,  H01C7/18

Abstract: A multilayer zinc oxide varistor without bismuth oxide system ingredients, and having variable breakdown voltages by controlling the thickness of the ceramic material; the varistor is bismuth-free and composed of zinc oxide as the primary constituent with alkaline earth element (Ba) as first additive, at least one of transition elements of Mn, Co, Cr, or Ni as second additives, at least one of rare earth elements of Pr, La, Ce, Nd or Tb as third additives and at least one of B, Si, Se, Al, Ti, W, Sn, Sb, Na, or K as rest additives, and the bismuth-free and zinc oxide based varistor exhibits an excellent ESD (Electro-Static Discharge) withstanding characteristic.

Abstract translation: 一种不含氧化铋体系成分的多层氧化锌压敏电阻，通过控制陶瓷材料的厚度具有可变的击穿电压; 所述变阻器是无铋的，以氧化锌为主要成分的碱土金属元素（Ba）作为第一添加剂，Mn，Co，Cr或Ni的过渡元素中的至少一种作为第二添加剂，至少一种稀有金属 作为第三添加剂的Pr，La，Ce，Nd或Tb的土元素，作为剩余添加剂的B，Si，Se，Al，Ti，W，Sn，Sb，Na或K中的至少一种， 基于氧化锌的变阻器具有优异的ESD（静电放电）耐受特性。